8位二进制全加器设计实验报告

EDA技术8位二进制全加器设计实验报告班级：学号：姓名：时间：2013-12-06目录TOC\o"1-3"\h\u28822方法一：自己写程序 230672一、设计原理 21472二、实验程序 312225程序1：半加器描述 314910程序2：一位二进制全加器设计顶层描述 313688程序3：D触发器描述 45924程序4：8位二进制加法器顶层描述 419907三、编译及仿真结果 921999方法二：使用LPM创立元件 1015494一、打开MegaWizardPlug-InManager 1016864二、按照提示，一步步完成全加器/全减器的创建 108995三、创建成功，生成CMP文件 105461四、调用CMP文件，例化元件，生成可以使用的元件。 1032510实验总结： 12摘要我在本实验中用顶层设计思想，用半加器、全加器、D触发器例化出八位全加器，完成了八路加法器、寄存器/锁存器的设计，上升沿触发，使用了6个数码管，分别用于显示输入A，输入B和输出，输出结果也用红灯进行了显示，溢出用绿灯表示。输入A用0~7号开关完成，输入B用10~17号开关完成，进位C用8号开关完成。实验要求完成八路全加器的设计，十六进制输出，上升沿触发，低电平复位，输入输出用数码管显示，用红灯显示输出，绿灯显示溢出。方法一：自己写程序一、设计原理先写一个半加器，然后用两个半加器例化出一个全加器，再用八个全加器例化出一个八位全加器。原理如图。关于上升沿触发，使用D触发器和八位全加器进行例化，D触发器接同一个时钟。最终完成上升沿触发的八位全加器的设计。二、实验程序程序1：半加器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_adderISPORT(A,B:INSTD_LOGIC; CO,SO:OUTSTD_LOGIC); ENDENTITYh_adder;ARCHITECTUREFH1OFh_adderISBEGIN SO<=NOT(AXOR(NOTB)); CO<=AANDB;ENDARCHITECTUREFH1;程序2：一位二进制全加器设计顶层描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_adderIS PORT(AIN,BIN,CIN:INSTD_LOGIC; COUT,SUM:OUTSTD_LOGIC);ENDENTITYf_adder;ARCHITECTUREFD1OFf_adderIS COMPONENTh_adderIS PORT(A,B:INSTD_LOGIC; CO,SO:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALD,E,F:STD_LOGIC;BEGIN U1:h_adderPORTMAP(A=>AIN,B=>BIN,CO=>D,SO=>E); U2:h_adderPORTMAP(A=>E,B=>CIN,CO=>F,SO=>SUM); COUT<=DORF;ENDARCHITECTUREFD1;程序3：D触发器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDEF1ISPORT(CLK:INSTD_LOGIC; D:INSTD_LOGIC; Q:OUTSTD_LOGIC);END;ARCHITECTUREbhvOFDEF1ISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1' THENQ1<=D;ENDIF; Q<=Q1;ENDPROCESS;ENDbhv;程序4：8位二进制加法器顶层描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_adder8ISPORT(AIN,BIN:INSTD_LOGIC_VECTOR(7DOWNTO0); ASEGIN1,ASEGIN2,BSEGIN1,BSEGIN2:BUFFERSTD_LOGIC_VECTOR(6DOWNTO0); CIN:INSTD_LOGIC; CLK:INSTD_LOGIC; SUM:BUFFERSTD_LOGIC_VECTOR(7DOWNTO0); SEG1:BUFFERSTD_LOGIC_VECTOR(6DOWNTO0); SEG2:BUFFERSTD_LOGIC_VECTOR(6DOWNTO0); COUT:OUTSTD_LOGIC);ENDf_adder8;ARCHITECTUREONEOFf_adder8IS COMPONENTf_adderIS PORT(AIN,BIN,CIN:INSTD_LOGIC; COUT,SUM:OUTSTD_LOGIC); ENDCOMPONENT; COMPONENTDEF1IS PORT(CLK:INSTD_LOGIC; D:INSTD_LOGIC; Q:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALC,C1,C2,C3,C4,C5,C6,C7:STD_LOGIC; SIGNALa:STD_LOGIC_VECTOR(7DOWNTO0); SIGNALb:STD_LOGIC_VECTOR(7DOWNTO0); SIGNALs:STD_LOGIC_VECTOR(7DOWNTO0); SIGNALss:STD_LOGIC_VECTOR(3DOWNTO0); SIGNALsss:STD_LOGIC_VECTOR(3DOWNTO0); BEGIN U1:f_adderPORTMAP(AIN=>a(0),BIN=>b(0),CIN=>CIN,SUM=>s(0),COUT=>C1); U2:f_adderPORTMAP(AIN=>a(1),BIN=>b(1),CIN=>C1,SUM=>s(1),COUT=>C2); U3:f_adderPORTMAP(AIN=>a(2),BIN=>b(2),CIN=>C2,SUM=>s(2),COUT=>C3); U4:f_adderPORTMAP(AIN=>a(3),BIN=>b(3),CIN=>C3,SUM=>s(3),COUT=>C4); U5:f_adderPORTMAP(AIN=>a(4),BIN=>b(4),CIN=>C4,SUM=>s(4),COUT=>C5); U6:f_adderPORTMAP(AIN=>a(5),BIN=>b(5),CIN=>C5,SUM=>s(5),COUT=>C6); U7:f_adderPORTMAP(AIN=>a(6),BIN=>b(6),CIN=>C6,SUM=>s(6),COUT=>C7); U8:f_adderPORTMAP(AIN=>a(7),BIN=>b(7),CIN=>C7,SUM=>s(7),COUT=>C); U9:DEF1PORTMAP(Q=>a(0),D=>AIN(0),CLK=>CLK); U10:DEF1PORTMAP(Q=>a(1),D=>AIN(1),CLK=>CLK); U11:DEF1PORTMAP(Q=>a(2),D=>AIN(2),CLK=>CLK); U12:DEF1PORTMAP(Q=>a(3),D=>AIN(3),CLK=>CLK); U13:DEF1PORTMAP(Q=>a(4),D=>AIN(4),CLK=>CLK); U14:DEF1PORTMAP(Q=>a(5),D=>AIN(5),CLK=>CLK); U15:DEF1PORTMAP(Q=>a(6),D=>AIN(6),CLK=>CLK); U16:DEF1PORTMAP(Q=>a(7),D=>AIN(7),CLK=>CLK); U17:DEF1PORTMAP(Q=>b(0),D=>BIN(0),CLK=>CLK); U18:DEF1PORTMAP(Q=>b(1),D=>BIN(1),CLK=>CLK); U19:DEF1PORTMAP(Q=>b(2),D=>BIN(2),CLK=>CLK); U20:DEF1PORTMAP(Q=>b(3),D=>BIN(3),CLK=>CLK); U21:DEF1PORTMAP(Q=>b(4),D=>BIN(4),CLK=>CLK); U22:DEF1PORTMAP(Q=>b(5),D=>BIN(5),CLK=>CLK); U23:DEF1PORTMAP(Q=>b(6),D=>BIN(6),CLK=>CLK); U24:DEF1PORTMAP(Q=>b(7),D=>BIN(7),CLK=>CLK); U25:DEF1PORTMAP(Q=>SUM(0),D=>s(0),CLK=>CLK); U26:DEF1PORTMAP(Q=>SUM(1),D=>s(1),CLK=>CLK); U27:DEF1PORTMAP(Q=>SUM(2),D=>s(2),CLK=>CLK); U28:DEF1PORTMAP(Q=>SUM(3),D=>s(3),CLK=>CLK); U29:DEF1PORTMAP(Q=>SUM(4),D=>s(4),CLK=>CLK); U30:DEF1PORTMAP(Q=>SUM(5),D=>s(5),CLK=>CLK); U31:DEF1PORTMAP(Q=>SUM(6),D=>s(6),CLK=>CLK); U32:DEF1PORTMAP(Q=>SUM(7),D=>s(7),CLK=>CLK); U33:DEF1PORTMAP(Q=>COUT,D=>C,CLK=>CLK); PROCESS(CLK,AIN,BIN) VARIABLEsSeg1:STD_LOGIC_VECTOR(7DOWNTO0); VARIABLEsSeg2:STD_LOGIC_VECTOR(7DOWNTO0); BEGIN ss(3DOWNTO0)<=SUM(3DOWNTO0); sss(3DOWNTO0)<=SUM(7DOWNTO4); sSeg1(7DOWNTO0):=AIN(7DOWNTO0); sSeg2(7DOWNTO0):=BIN(7DOWNTO0); CASEssIS WHEN"0000"=>SEG1<="1000000";--0 WHEN"0001"=>SEG1<="1111001"; WHEN"0010"=>SEG1<="0100100"; WHEN"0011"=>SEG1<="0110000"; WHEN"0100"=>SEG1<="0011001"; WHEN"0101"=>SEG1<="0010010"; WHEN"0110"=>SEG1<="0000010"; WHEN"0111"=>SEG1<="1111000"; WHEN"1000"=>SEG1<="0000000"; WHEN"1001"=>SEG1<="0011000";--9 WHEN"1010"=>SEG1<="0001000"; WHEN"1011"=>SEG1<="0000011"; WHEN"1100"=>SEG1<="1001110"; WHEN"1101"=>SEG1<="0100001"; WHEN"1110"=>SEG1<="0000110"; WHEN"1111"=>SEG1<="0001110"; WHENOTHERS=>NULL; ENDCASE; CASEsssIS WHEN"0000"=>SEG2<="1000000";--0 WHEN"0001"=>SEG2<="1111001"; WHEN"0010"=>SEG2<="0100100"; WHEN"0011"=>SEG2<="0110000"; WHEN"0100"=>SEG2<="0011001"; WHEN"0101"=>SEG2<="0010010"; WHEN"0110"=>SEG2<="0000010"; WHEN"0111"=>SEG2<="1111000"; WHEN"1000"=>SEG2<="0000000"; WHEN"1001"=>SEG2<="0011000";--9 WHEN"1010"=>SEG2<="0001000"; WHEN"1011"=>SEG2<="0000011"; WHEN"1100"=>SEG2<="1001010"; WHEN"1101"=>SEG2<="0100001"; WHEN"1110"=>SEG2<="0000110"; WHEN"1111"=>SEG2<="0001110"; WHENOTHERS=>NULL; ENDCASE; CASEsSeg1(3DOWNTO0)IS WHEN"0000"=>ASEGIN1<="1000000";--0 WHEN"0001"=>ASEGIN1<="1111001"; WHEN"0010"=>ASEGIN1<="0100100"; WHEN"0011"=>ASEGIN1<="0110000"; WHEN"0100"=>ASEGIN1<="0011001"; WHEN"0101"=>ASEGIN1<="0010010"; WHEN"0110"=>ASEGIN1<="0000010"; WHEN"0111"=>ASEGIN1<="1111000"; WHEN"1000"=>ASEGIN1<="0000000"; WHEN"1001"=>ASEGIN1<="0011000";--9 WHEN"1010"=>ASEGIN1<="0001000"; WHEN"1011"=>ASEGIN1<="0000011"; WHEN"1100"=>ASEGIN1<="1001010"; WHEN"1101"=>ASEGIN1<="0100001"; WHEN"1110"=>ASEGIN1<="0000110"; WHEN"1111"=>ASEGIN1<="0001110"; WHENOTHERS=>NULL; ENDCASE; CASEsSeg1(7DOWNTO4)IS WHEN"0000"=>ASEGIN2<="1000000";--0 WHEN"0001"=>ASEGIN2<="1111001"; WHEN"0010"=>ASEGIN2<="0100100"; WHEN"0011"=>ASEGIN2<="0110000"; WHEN"0100"=>ASEGIN2<="0011001"; WHEN"0101"=>ASEGIN2<="0010010"; WHEN"0110"=>ASEGIN2<="0000010"; WHEN"0111"=>ASEGIN2<="1111000"; WHEN"1000"=>ASEGIN2<="0000000"; WHEN"1001"=>ASEGIN2<="0011000";--9 WHEN"1010"=>ASEGIN2<="0001000"; WHEN"1011"=>ASEGIN2<="0000011"; WHEN"1100"=>ASEGIN2<="1001010"; WHEN"1101"=>ASEGIN2<="0100001"; WHEN"1110"=>ASEGIN2<="0000110"; WHEN"1111"=>ASEGIN2<="0001110"; WHENOTHERS=>NULL; ENDCASE; CASEsSeg2(3DOWNTO0)IS WHEN"0000"=>BSEGIN1<="1000000";--0 WHEN"0001"=>BSEGIN1<="1111001"; WHEN"0010"=>BSEGIN1<="0100100"; WHEN"0011"=>BSEGIN1<="0110000"; WHEN"0100"=>BSEGIN1<="0011001"; WHEN"0101"=>BSEGIN1<="0010010"; WHEN"0110"=>BSEGIN1<="0000010"; WHEN"0111"=>BSEGIN1<="1111000"; WHEN"1000"=>BSEGIN1<="0000000"; WHEN"1001"=>BSEGIN1<="0011000";--9 WHEN"1010"=>BSEGIN1<="0001000"; WHEN"1011"=>BSEGIN1<="0000011"; WHEN"1100"=>BSEGIN1<="1001010"; WHEN"1101"=>BSEGIN1<="0100001"; WHEN"1110"=>BSEGIN1<="0000110"; WHEN"1111"=>BSEGIN1<="0001110"; WHENOTHERS=>NULL; ENDCASE; CASEsSeg2(7DOWNTO4)IS WHEN"0000"=>BSEGIN2<="1000000";--0 WHEN"0001"=>BSEGIN2<="1111001"; WHEN"0010"=>BSEGIN2<="0100100"; WHEN"0011"=>BSEGIN2<="0110000"; WHEN"0100"=>BSEGIN2<="0011001"; WHEN"0101"=>BSEGIN2<="0010010"; WHEN"0110"=>BSEGIN2<="0000010"; WHEN"0111"=>BSEGIN2<="1111000"; WHEN"1000"=>BSEGIN2<="0000000"; WHEN"1001"=>BSEGIN2<="0011000";--9 WHEN"1010"=>BSEGIN2<="0001000"; WHEN"1011"=>BSEGIN2<="0000011"; WHEN"1100"=>BSEGIN2<="1001110"; WHEN"1101"=>BSEGIN2<="0100001"; WHEN"1110"=>BSEGIN2<="0000110"; WHEN"1111"=>BSEGIN2<="0001110"; WHENOTHERS=>NULL; ENDCASE; ENDPROCESS; --U1:f_adderPORTMAP(AIN=>AIN(0),BIN=>BIN(0),CIN=>CIN,SUM=>SUM(0),COUT=>C1); --U2:f_adderPORTMAP(AIN=>AIN(1),BIN=>BIN(1),CIN=>C1,SUM=>SUM(1),COUT=>C2); --U3:f_adderPORTMAP(AIN=>AIN(2),BIN=>BIN(2),CIN=>C2,SUM=>SUM(2),COUT=>C3); --U4:f_adderPORTMAP(AIN=>AIN(3),BIN=>BIN(3),CIN=>C3,SUM=>SUM(3),COUT=>C4); --U5:f_adderPORTMAP(AIN=>AIN(4),BIN=>BIN(4),CIN=>C4,SUM=>SUM(4),COUT=>C5); --U6:f_adderPORTMAP(AIN=>AIN(5),BIN=>BIN(5),CIN=>C5,SUM=>SUM(5),COUT=>C6); --U7:f_adderPORTMAP(AIN=>AIN(6),BIN=>BIN(6),CIN=>C6,SUM=>SUM(6),COUT=>C7); --U8:f_adderPORTMAP(AIN=>AIN(7),BIN=>BIN(7),CIN=>C7,SUM=>SUM(7),COUT=>COUT);ENDONE;三、编译及仿真结果程序波形仿真图时间分析方法二：使用LPM创立元件一