雨课堂学堂在线学堂云数字逻辑电路安徽新华学院单元测试考核答案

注：不含主观题第1题Aquantityhavingdiscretenumericalvaluesis()AananalogquantityBadigitalquantityCabinaryquantityDanaturalquantity第2题Thetimeintervalbetweenthe50%pointsontherisingandfallingedgesis()ArisetimeBfalltimeCpulsewidthDperiod第3题Apulseinacertainwaveformhasafrequencyof50Hz.Itrepeatsitselfevery()A1msB20msC50msD100ms第4题Inacertaindigitalwaveform,theperiodisfourtimesthepulsewidth.Thedutycycleis()A25%B50%C75%D100%第5题5．Thetermbitmeans（

）AOctaldigitBDecimalbit

CHexadecimalbitDBinarydigit第6题Ananalogquantityisonehavingcontinuousvalues.()第7题Adigitalquantityhasnodiscretevalues.()第8题Therearetwodigitsinthebinarysystem.()第9题Thetermbitisshortforbinarydigit.()第10题Inpositivelogic,aLOWlevelrepresentsabinary1.()第11题Aperiodicwaverepeatsitselfatafixedinterval.()第12题Atimingdiagramshowsthetimingrelationshipoftwoormoredigitalwaveforms.()第13题AnANDfunctionisimplementedbyalogiccircuitknownasaninverter.()第14题Aflip-flopisabistablelogiccircuitthatcanstoreonlytwobitsatatime.()第15题Twobroadtypesofdigitalintegratedcircuitsarefixed-functionandprogrammable.()2Test2第1题1．Thebinarynumber101100111001010100001canbewritteninoctalas（B）AA．54712308BB．54712418CC．26345218DD．231625018第2题Thebinarynumber10001101010001101111canbewritteninhexadecimalas（）AA．AD46716BB．8C46F16CC．8D46F16DD．AE46F16第3题ThebinarynumberforF7A916is（

）AA．1111011110101001BB．1110111110101001CC．1111111010110001DD．1111011010101001第4题TheBCDnumberfordecimal473is()A111011010B110001110011C010001110011D010011110011第5题RefertoTable.ThecommandSTOPinASCIIis()A1010011101010010011111010000B1010010100110010011101010000C1001010110110110011101010001D1010011101010010011101100100第6题Theoctalnumbersystemisaweightedsystemwitheightdigits.()第7题Thebinarynumbersystemisaweightedsystemwithtwodigits.()第8题MSBstandsformostsignificantbit.()第9题Inhexadecimal,9+1=10.()第10题The1’scomplementofthebinarynumber1010is0101.()第11题The2’scomplementofthebinarynumber1111is0000.()第12题Theright-mostbitinasignedbinarynumberisthesignbit.()第13题Thehexadecimalnumbersystemhas16characters,sixofwhicharealphabeticcharacters.()第14题BCDstandsforbinarycodeddecimal.()第15题Anerrorinagivencodecanbedetectedbyverifyingtheparitybit.()第16题CRCstandsforcyclicredundancycheck.()第17题Themodulo-2sumof11and10is100.()第18题Thebinarynumber1111isequaltothedecimalnumber16.()Test3第1题AvariableisasymbolinBooleanalgebrausedtorepresent()AdataBaconditionCanactionDanswers(a),(b),and(c)第2题TheBooleanexpressionA+B+Cis()AasumtermBaliteraltermCaninversetermDaproductterm第3题TheBooleanexpressionA’BC’Dis()AasumtermBaliteraltermCaninversetermDaproductterm第4题ThedomainoftheexpressionAB’CD+AB’+C’D+Bis()AAandDBBonlyCA,B,C,andDDnoneofthese第5题Accordingtotheassociativelawofaddition,()AA．A+B=B+ABB．A=A+ACC．(A+B)+C=A+(B+C)DD．A+0=A第6题Variable,complement,andliteralarealltermsusedinBooleanalgebra.()第7题AdditioninBooleanalgebraisequivalenttotheNORfunction.()第8题MultiplicationinBooleanalgebraisequivalenttotheANDfunction.()第9题Thecommutativelaw,associativelaw,anddistributivelawarealllawsinBooleanalgebra.()第10题Thecomplementof0is0itself.()第11题WhenaBooleanvariableismultipliedbyitscomplement,theresultisthevariable()第12题“Thecomplementofaproductofvariablesisequaltothesumofthecomplementsofeachvariable”isastatementofDeMorgan’stheorem.()第13题SOPmeanssum-of-products.()第14题KarnaughmapscanbeusedtosimplifyBooleanexpressions.()第15题A3-variableKarnaughmaphassixcells.()第16题VHDLisatypeofhardwaredefinitionlanguage.()第17题AVHDLprogramconsistsofanentityandanarchitecture.(

)Test4第1题WhentheinputtoaninverterisLOW(0),theoutputis()AHIGHor0BLOWor0CHIGHor1DLOWor1第2题2．Aninverterperformsanoperationknownas（）AcomplementationBassertionCinversionDand正确答案：AC第3题3.TheoutputofanANDgatewithinputsA,BandCis0(LOW)when（

)AA=0,B=0,C=0BA=0,B=1,C=1C

bothanswers(A)and(B)DA=1,B=1,C=1第4题TheoutputofanORgatewithinputsA,BandCis0()when()AA=0,B=0,C=0BA=0,B=1,C=1CA=1,B=0,C=1DA=1,B=1,C=0第5题Apulseisappliedtoeachinputofa2-inputNANDgate.OnepulsegoesHIGHatt=0andgoesbackLOWatt=1ms.TheotherpulsegoesHIGHatt=0.8msandgoesbackLOWatt=3ms.Theoutputpulsecanbedescribedasfollows:()AItgoesLOWatt=0andbackHIGHatt=3ms.BItgoesLOWatt=0.8msandbackHIGHatt=3ms.CItgoesLOWatt=0.8msandbackHIGHatt=1ms.DItgoesLOWatt=0.8msandbackLOWatt=1ms.第6题Tomeasuretheperiodofapulsewaveform,youmustuse()AaDMMBalogicprobeCanoscilloscopeDalogicpulser第7题Onceyoumeasuretheperiodofapulsewaveform,thefrequencyisfoundby()AusinganothersettingBmeasuringthedutycycleCfindingthereciprocaloftheperiodDusinganothertypeofinstrument第8题AninverterperformsaNOToperation.()第9题ANOTgatecannothavemorethanoneinput.()第10题IfanyinputtoanORgateiszero,theoutputiszero.()第11题IfallinputstoanANDgateare1,theoutputis0.()第12题ANANDgatecanbeconsideredasanANDgatefollowedbyaNOTgate.()第13题ANORgatecanbeconsideredasanORgatefollowedbyaninverter.()第14题Theoutputofanexclusive-ORis0iftheinputsareopposite.()第15题Twotypesoffixed-functionlogicintegratedcircuitsarebipolarandNMOS.()第16题Onceprogrammed,PLDlogiccanbechanged.()第17题10.Fan-outisthenumberofsimilargatesthatagivengatecandrive.Test5第1题Ahalf-adderischaracterizedby()AtwoinputsandtwooutputsBthreeinputsandtwooutputsCtwoinputsandthreeoutputsDtwoinputsandoneoutput第2题Afull-adderischaracterizedby()AtwoinputsandtwooutputsBthreeinputsandtwooutputsCtwoinputsandthreeoutputsDtwoinputsandoneoutput第3题TheinputstoafulladderareA=1,B=0,Cin=1.Theoutputsare()ASum=0,Cout=1BSum=1,Cout=0CSum=0,Cout=0DSum=1,Cout=1第4题A3-bitparalleladdercanadd()Athree2-bitbinarynumbersBtwo3-bitbinarynumbersCthreebitsatatimeDthreebitsinsequence第5题Toexpanda2-bitparalleladdertoa4-bitparalleladder,youmust:()Ausetwo2-bitadderswithnointerconnections.Busetwo2-bitaddersandconnectthesumoutputsofonetothebitinputsoftheother.Cusefour2-bitadderswithnointerconnections.Dusetwo2-bitadderswiththecarryoutputofoneconnectedtothecarryinputoftheother.第6题Ifa74HC85magnitudecomparatorhasA=1000andB=1010,theoutputsare()AA>BBA<BCA=B第7题Ifa1-of-16decoderwithactive-LOWoutputsexhibitsaLOWonthedecimal12output,whataretheinputs()AA3A2A1A0=1010BA3A2A1A0=1110CA3A2A1A0=1100DA3A2A1A0=0100第8题ABCD-to-7segmentdecoderhas0100onitsinputs.Theactiveoutputsare()Aa,c,f,gBb,c,f,gCb,c,e,fDb,d,e,g第9题Ifanoctal-to-binarypriorityencoderhasits0,2,5,and6inputsattheactivelevel,theactiveHIGHbinaryoutputis()A110B010C101D000第10题Ingeneral,amultiplexerhas()Aonedatainput,severaldataoutputs,andselectioninputsBonedatainput,onedataoutput,andoneselectioninputCseveraldatainputs,severaldataoutputs,andselectioninputsDseveraldatainputs,onedataoutput,andselectioninputs第11题Ahalf-adderaddstwobinarybits.()第12题Ahalf-adderhasacarryoutputonly.()第13题Afulladderaddstwobitsandproducestwooutputs.()第14题Afull-addercanberealizedonlybyusing2-inputXORgates.()第15题Whentheinputbitsareboth1andtheinputcarrybitis1,thesumoutputofafulladderis1.()第16题Theoutputofacomparatoris0whenthetwobinaryinputsgivenareequal.()第17题Adecoderdetectsthepresenceofaspecifiedcombinationofinputbits.()第18题The4-line-to-10-linedecoderandthe1-of-10decoderaretwodifferenttypes.()第19题Anencoderessentiallyperformsareversedecoderfunction.()第20题Amultiplexerisalogiccircuitthatallowsdigitalinformationfromasinglesourcetoberoutedontoseverallines.()4Test6第1题AnactiveHIGHinputS-Rlatchisformedbythecross-couplingof()AtwoNORgatesBtwoNANDgatesCtwoORgatesDtwoANDgates第2题WhichofthefollowingisnottrueforanactiveLOWinputS’-R’latch()AS’=1,R‘=1,Q=NC,Q’=NCBS’=0,R‘=1,Q=1,Q’=0CS‘=1,R’=0,Q=1,Q’=0DS’=0,R‘=0,Q=1,Q’=1第3题ForwhatcombinationsoftheinputsDandENwillaDlatchreset()AD=LOW,EN=LOWBD=LOW,EN=HIGHCD=HIGH,EN=LOWDD=HIGH,EN=HIGH第4题Thepurposeoftheclockinputtoaflip-flopisto()AclearthedeviceBsetthedeviceCalwayscausetheoutputtochangestatesDcausetheoutputtoassumeastatedependentonthecontrolling(J-KorD)inputs.第5题5．Foranedge-triggeredDflip-flop（

）Aachangeinthestateoftheflip-flopcanoccuronlyataclockpulseedgeBthestatethattheflip-flopgoestodependsontheDinputCtheoutputfollowstheinputateachclockpulseDalloftheseanswers第6题AfeaturethatdistinguishestheJ-Kflip-flopfromtheDflip-flopisthe()AtoggleconditionBpresetinputCtypeofclockDclearinput第7题Aflip-flopisSETwhen()AJ=0,K=0BJ=0,K=1CJ=1,K=0DJ=1,K=1第8题AJ-Kflip-flopwithJ=1andK=1hasa10kHzclockinput.TheQoutputis()AconstantlyHIGHBconstantlyLOWCa10kHzsquarewaveDa5kHzsquarewave第9题Alatchhasonestablestate.()第10题AlatchisconsideredtobeintheRESETstatewhentheQoutputislow()第11题AgatedDlatchcannotbeusedtochangestate.()第12题Flip-flopsandlatchesarebothbistabledevices.()第13题Anedge-triggeredDflip-flopchangesstatewhenevertheDinputchanges.()第14题Aclockinputisnecessaryforanedge-triggeredflip-flop.()第15题WhenboththeJandKinputsareHIGH,anedge-triggeredJ-Kflip-flopchangesstateoneachclockpulse.()第16题Aone-shotisalsoknownasanastablemultivibrator.(

)第17题Whentriggered,aone-shotproducesasinglepulse.()第18题The555timercannotbeusedasapulseoscillator.(

)

Test7第1题Aregister’sfunctionsinclude()AdatastorageBdatamovementCneither(A)not(B)Dboth(A)and(B)第2题Toparallelloadabyteofdataintoashiftregisterwithasynchronousload,theremustbe()AoneclockpulseBoneclockpulseforeach1inthedataCeightclockpulsesDoneclockpulseforeach0inthedata第3题Thegroupofbits10110101isseriallyshifted(right-mostbitfirst)intoan8-bitparalleloutputshiftregisterwithaninitialstateof11100100.Aftertwoclockpulses,theregistercontains()A01011110B10110101C01111001D00101101第4题Witha100kHzclockfrequency,eightbitscanbeseriallyenteredintoashiftregisterin()A80usB8msC80msD10ms第5题Witha1MHzclockfrequency,eightbitscanbeparallelenteredintoashiftregister()Ain8msBinthepropagationdelaytimeofeightflip-flopsCin1msDinthepropagationdelaytimeofoneflip-flop第6题Amodulus-8Johnsoncounterrequires()Aeightflip-flopsBfourflip-flopsCfiveflip-flopsDtwelveflip-flops第7题Amodulus-8ringcounterrequires()Aeightflip-flopsBfourflip-flopsCfiveflip-flopsDtwelveflip-flops第8题Whenan8-bitserialin/serialoutshiftregisterisusedfora24mstimedelay,theclockfrequencymustbe()A41.67kHzB333kHzC125kHzD8MHz第9题Shiftregistersconsistofanarrangementofflip-flops.()第10题Ashiftregistercannotbeusedtostoredata.()第11题Aserialshiftregisteracceptsonebitatatimeonasingleline.()第12题Allshiftregistersaredefinedbyspecifiedsequences.()第13题Ashiftregistercounterisashiftregisterwiththeserialoutputconnectedbacktotheserialinput.()第14题Ashiftregisterwithfourstagescanstoreamaximumcountoffifteen.()第15题TheJohnsoncounterisaspecialtypeofshiftregister.()第16题Themodulusofan8-bitJohnsoncounteriseight.()第17题Aringcounterusesoneflip-flopforeachstateinitssequence.()第18题Ashiftregistercannotbeusedasatimedelaydevice.()

第19题2．Toenterabyteofdataseriallyintoan8-bitshiftregister,theremustbe（

)

AoneclockpulseBtwoclockpulsesC

fourclockpulsesDeightclockpulsesTest8第1题Adecadecounterwithacountofzero(0000)throughnine(1001)isknownas()AanASCIIcounterBabinarycounterCABCDcounterDadecimalcounter第2题Themodulusofacounteris

(

)Athenumberofflip-flopsBtheactualnumberofstatesinitssequenceCthenumberoftimesitrecyclesinasecondDthemaximumpossiblenumberofstates第3题A3-bitbinarycounterhasamaximummodulusof()A3B6C8D16第4题A5-bitbinarycounterhasamaximummodulusof()A4B8C16D32第5题Amodulus-12countermusthave()A12flip-flopsB3flip-flopsC4flip-flopsDsynchronousclocking第6题Whichoneofthefollowingisanexampleofacounterwithatruncatedmodulus()AModulus8BModulus14CModulus16DModulus32第7题A4-bitripplecounterconsistsofflip-flopsthateachhaveapropagationdelayfromclocktoQo