IBM PCAT 硬件架构与动作原理.ppt

1、1,IBM PC/AT 硬體架構與動作原理,(1).PC/AT Original Schematics 1.The Blocks Structure 2.Decoder 3.Data Bus Flow 4.Address Bus Flow 5.Other Signals and ISA (2).KT9 System( ATI RS200MP+ALI M1535+ ) 1.System Block Diagram 2.System Start Steps 3.POST(Power-On Self Test) 4.BIOS,(3).Differences (versus CPU/PCI /ISA)

2、 1.Introduction 2.CPU Bus Cycle 3.PCI (4).Introduction the Compact PCI,by JR Jen 01-12-05 Hom Wo 03-12-29,2,IBM PC/AT 原版電路之功能方塊的內容,1.系統時脈電路 2.DRAM解碼電路 3.RAS&CAS產生電路 4.DRAM偵測電路 5.DRAM定址電路 6.ROM Access電路 7.Decoder 8.等待電路 9.刷新要求電路,10.DMA 控制電路 11.系統中斷電路 12.系統計時/計數器電路 13.鍵盤控制器電路 14.及時時脈電路 15.NMI控制電路 16.S

3、hut-down Logic,3,Figure : Decoder(PC/AT original schematic),4,5,IBM PC/AT IO Port Addresses,1. Range 00HFFH : System board 2. Range 1003FFH : I/O Channel 3. 00H1FH : DMA Controller 1 Registers 4. 20H3FH : Interrupt Controller 1 Register 5. 40H5FH : Programmable Interrupt Timer 6. 60H64H : keyboard C

4、ontroller buffer 7. 70H : CMOS RAM address register port,6,8. 71H : CMOS RAM data register Port 9. 80H : Manufacturing Test Port 10. 81H8FH : DMA page table address reg. 11. A0HBFH : Programmable interrupt ctrl 2 12. C0HDFH : DMA Controller 2 Register 13. F0HFFH : Math Coprocessor regs. 14. 170H177H

5、 : Fixed disk 1 registers 15. 1F0H1F7H : Fixed disk 0 registers 16. 200H20FH : Game control port 17. 201H : Game Port I/O Data 18. 278H27AH : Parallel Port 3 registers 19.2F8H2FFH : Serial Port 2 registers,7,20. 370H377H : Diskette Controller 1 reg 21. 378H37AH : Parallel Port 2 registers 22. 3BCH3B

6、EH : Parallel Port 1 registers 23. 3F0H3FFH : Diskette Controller 0 reg 24. 3F8H3FFH : Serial Port 1 registers 25. 3C0H3CFH : VGA I/O Port registers,8,8042 Control Register(I/O Port Address : 61H),Read/Write status Bit 7 =1 Parity check Bit 6 =1 Channel check Bit 5 =1 Timer 2 output Bit 4 =1 Toggle

7、with each refresh request Bit 3 =1 Channel check enabled Bit 2 =1 Parity check enabled Bit 1 =1 Speak data enabled Bit 0 =1 Timer 2 gate to speaker enabled,9,10,11,外在緩衝器控制線路,外在緩衝器,External Buffer的OIR控制得分析,12,SA0SA19,13,HLDA,65,U74,80286,ALE,5,U83,82288,RESET,12,U82,82284,11,12,13,U11,ALS08,4,5,6,U80

8、,ALS32,Y,5,Y,7,Y,3,Y,9,A15,10,A,13,A,17,A,11,G,19,U75,ALS244,CPU HLDA,HLDA,-MASTER,ALE,+ACK,GATE ALE,+RESET,HLDA,AEN,BALE,RESET DRV,AEN, BALE, RESET DRV : AT Slot signals.,AEN, BALE, RESET DRV 信號的流程,From AT slot,HLDA,14,15,16,17,KT9 System Block Diagram,18,KT9 Power On Block Diagram,19,System Start

9、Steps (1),1. Power ON/OFF Button PC87570(PCU) 2. PC87570 M1535+(South Bridge) 3. M1535+ PC87570 SUS Power(3VSUS、5VSUS) 4. PC87570 Main Power(3V、5V、2.5V) VHcore,20,1. When we push the Power Button, the signal -NBSWON will be generated and send to the PCU(PC87570). 2. As the PCU receives the -NBSWON,

10、it will send the -DNBSWON to the south bridge(M1535+). 3. Then the SB asserts -SUSB and -SUSC signals to the PCU. 4. The PCU will send the SUSON, MAINON and VRON for suspend power, main power and VHcore generating.,System Start Steps (1),21,4.1 PC87570,SUSON,2.5VSUS,12VS,3VSUS,5VSUS,4.2 PC87570,MAIN

11、ON,3VAGP,2.5V,12V,VTT_DDR,3V,5V,SUSD,MAIND,4.3 PC87570,-VRON,2.5VSUS,VHcore,22,System Start Steps (2),HWPG,5. MAX1632,HWPG-POWER,PC87570,6. PC87570,NPWROK,NB_PWROK,RS200MP (NB),NB_PWROK,PWROK,7.,SB_PWROK,M1535+,CPU_PWRGD,PWRGOOD,CPU,23,System Start Steps (3),-SYS_RST,8. M1535+,-PCI_RST,-PCI_RST,9.,-

12、NB_PCIRST,RS200MP,SB_PWROK,-PCIRST,10. RS200MP,-CPU_RST,CPU,* CPU and all I/O devices have been reset.,24,System Start Steps (4),11. CPU Memory Code Read North Bridge - Address (A31# A3#) : FFFF FFF0 12. North Bridge : CPU Command PCI Command CPU Address PCI Address 13. North Bridge Memory Read Sout

13、h Bridge - Address ( AD31 AD0) : FFFF FFF0 14. South Bridge : PCI Command ISA Command PCI Address ISA Address,25,System Start Steps (4),11. CPU will generate the first command- Memory Code Read to the North Bridge, and the Host address - (A31# A3#) : FFFF FFF0. 12. When the NB receives the CPU comma

14、nd and Host address, It will translate the CPU command to PCI command-(Memory Read), and translate the Host Address to the PCI address-(AD31#AD0#):FFFF FFF0. 13. Then the NB sends the PCI command and PCI address to the South Bridge via the PCI Bus. 14. AS the SB receives the PCI command and PCI addr

15、ess, it will translate the PCI command to the ISA command-(MEMR#) and the PCI address to the ISA address-(A19A0):FFFFF.,26,System Start Steps (5),15. South Bridge MEMR# System ROM - Address ( SA17 SA0 ): 1FFF0 16. ROM Data ISA Data Bus South Bridge 17. South Bridge PCI Data Bus North Bridge 18. Nort

16、h Bridge Host Data Bus CPU 19. CPU: Decode and Execute (Go To Step 11 : Decode & Execute),27,System Start Steps (5),15. THE SB will drive the MEMR# command to the System ROM and access the ROM address ( SA17 SA0 ): 1FFF0 16. So the ROM Data will be transferred to South Bridge through the ISA Bus 17.

17、 And then through the PCI Bus, the South Bridge will send the PCI date to the North Bridge 18. At the last the North Bridge will send Host data to the CPU through the Host Bus. 19. After the CPU fetch the host data which is transferred from North Bridge, it begins to Decode & Execute(Go To Step 11 :

18、 Decode & Execute).,28,The first Execution Instruction in PC AT,CPU Address : A31 A3 = FFFF FFF0 CPU : CS: IP = F000:FFF0 FFFF0 ISA Address : SA17 SA0 = 1FFF0 ISA Data : 1FFF0: EA 5B E0 00 F0 30 37 2F 1FFF8: 31 35 2F 39 39 00 FC 00 5.EA 5B E0 00 F0 = Long Jump F000:E05B 30 37 2F 31 35 2F 39 39 = 07/

19、15/99,29,POST (Power-On Self Test) Process,POST tests and initializes the following : The central processing unit ( CPU ) The ROM BIOS ( checksum ) The CMOS RAM The Intel 8237 DMA Controller The keyboard controller The base 64K System RAM The Programmable Interrupt controller,30,8. The Programmable

20、Interrupt Timer 9. The cache controller 10. COMS RAM configuration data 11.The CRT controller 12. RAM memory above 64K 13. The keyboard 14. Diskette drive A availability 15. The serial interface circuitry 16. The diskette controller 17. The fixed disk controller 18. Any additional hardware,31,AWARD

21、BIOS POST Test code listing,32,33,34,IBM PC/AT System RAM Data Area,(1). Range : 00H to 3FFH Interrupt Vector Table Interrupt Vector Stored as offset/segment format (2). Range : 400H to 4FFH BIOS Data Area Data definitions related to BIOS fixed disk , diskette , Keyboard , video , ,35,The first two

22、words of expansion ROM area,VGA BIOS (CS:IP = C000:0000) ROM Byte Value 0 55H 1 AAH 2 ROM Length in 512-byte blocks 3 Entry point for ROM initialization ( via FAR CALL ),36,Differences (vs. CPU / PCI /ISA ),CPU PCI ISA 1. Speed 66/100/133 33/66 8 MHz 2. Power Vcore & Vio 3.3V 5V 3. Address Bus 32 /

23、(36) 32/64 24 bit 4. Data Bus 64 32/64 16 bit 5. Address/Data Separate Shared Separate,37,6. Control Bus ( Commands / Control signals ) CPU PCI ISA 6.1 Types 8/(32) 16 4 6.2 Start ADS- FRAME- BALE 6.3 End Ready- IRDY-&TRDY- IOCHRDY 7. ID VPID0:3 IDSEL- ( Decoder ),38,39,BUS CYCLE DEFINITION,40,Trans

24、action Type Defined by REQ# Signals,41,Table LEN1:0# Signal Data Transfer Lengths,Table ASZ1:0# Signal Decode,42,POWERGOOD Relationship at Power-On,VCCcore,VCCL2,PWRGOOD,RESET#,Clock,1 ms,Ratio,BCLK,43,System Bus To Core Frequency Multiplier Configuration,44,45,ADDRESS PHASE,DATA PHASE,DATA PHASE,DA

25、TA PHASE,BUS TRANSACTION,Figure : Basic Read Operation,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-2,DATA-3,C/BE#,BUS CMD,BE#S,IRDY#,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,TRDY#,DEVSEL#,46,Command Definition,C/BE3:0# Command Type 0000 Interrupt Acknowledge 0001 Special Cycl

26、e 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate,47,DATA PHASE,DATA PHASE,DATA PHASE,BUS TRANSACTION,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-3,C/BE#,BUS CMD,BE#S-3,IRDY#,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,TRDY#,DEVSEL#,DATA-2,BE#S-1,BE#S-2,ADDRESS PHASE,Figure : Basic Write Operation,48,PCI COMPLIANT DEVICE,AD