硬件接口（一）GPIO实验

1、硬件接口（一）gpio实验c54xx.h view code 1 /*/ 2 /* title: c54xx.h */ 3 /* version: 1.0 */ 4 /* author: zzh */ 5 /* data: 2005-08-20 */ 6 /*/ 7 8 ifndef _c54xx_h_ 9 define _c54xx_h_ 10 11 include std.h 12 13 define uint unsigned int 14 define uchar unsigned char 15 define ulong unsigned long 16 define ushort

2、unsigned short 17 define vuint volatile unsigned int 18 ifndef null 19 define null 0 20 define false (bool)0 21 define true (bool)1 22 endif 23 24 /*/ 25 /* cpu memory-mapped registers */ 26 /*/ 27 28 /* interrupt flag and interrupt mask registers */ 29 define imr *(vuint *)0x00 30 define imr_addr 0

3、x00 31 define ifr *(vuint *)0x01 32 define ifr_addr 0x01 33 34 /* status registers */ 35 define st0 *(vuint *)0x06 36 define st0_addr 0x06 37 define st1 *(vuint *)0x07 38 define st1_addr 0x07 39 40 /* accumulator registers */ 41 define al *(vuint *)0x08 42 define al_addr 0x08 43 define ah *(vuint *)

4、0x09 44 define ah_addr 0x09 45 define ag *(vuint *)0x0a 46 define ag_addr 0x0a 47 define bl *(vuint *)0x0b 48 define bl_addr 0a0b 49 define bh *(vuint *)0x0c 50 define bh_addr 0x0c 51 define bg *(vuint *)0x0d 52 define bg_addr 0x0d 53 54 /* temporary register */ 55 define t *(vuint *)0x0e 56 define

5、t_addr 0x0e 57 58 /* transition register */ 59 define trn *(vuint *)0x0f 60 define trn_addr 0x0f 61 62 /* auxiliary registers */ 63 define ar0 *(vuint *)0x10 64 define ar0_addr 0x10 65 define ar1 *(vuint *)0x11 66 define ar1_addr 0x11 67 define ar2 *(vuint *)0x12 68 define ar2_addr 0x12 69 define ar

6、3 *(vuint *)0x13 70 define ar3_addr 0x13 71 define ar4 *(vuint *)0x14 72 define ar4_addr 0x14 73 define ar5 *(vuint *)0x15 74 define ar5_addr 0x15 75 define ar6 *(vuint *)0x16 76 define ar6_addr 0x16 77 define ar7 *(vuint *)0x17 78 define ar7_addr 0x17 79 80 /* stack pointer register */ 81 define sp

7、 *(vuint *)0x18 82 define sp_addr 0x18 83 84 /* circular buffer size register */ 85 define bk *(vuint *)0x19 86 define bk_addr 0x19 87 88 /* block repeat counter */ 89 define brc *(vuint *)0x1a 90 define brc_addr 0x1a 91 92 /* block repeat start end aress */ 93 define rsa *(vuint *)0x1b 94 define rs

8、a_addr 0x1b 95 define rea *(vuint *)0x1c 96 define rea_addr 0x1c 97 98 /* processor mode status register */ 99 define pmst *(vuint *)0x1d100 define pmst_addr 0x1d101 102 /* extended program page register */103 define xpc *(vuint *)0x1e104 define xpc_addr 0x1e105 106 /*/107 /* peripheral memory-mappe

9、d registers */108 /*/109 110 /* timer registers */111 define tim *(vuint *)0x24 112 define tim_addr 0x24113 define prd *(vuint *)0x25114 define prd_addr 0x25115 define tcr *(vuint *)0x26116 define tcr_addr 0x26117 118 /* software wait-e control registers */119 define swwsr *(vuint *)0x28120 define s

10、wwsr_addr 0x28121 define swcr *(vuint *)0x2b122 define swcr_addr 0x2b123 124 /* bank-switching control register */125 define bscr *(vuint *)0x29126 define bscr_addr 0x29127 128 /* hpi control register */129 define hpic *(vuint *)0x2c130 define hpic_addr 0x2c131 132 /* registers of mcbsp receive and

11、transmit*/133 typedef volatile struct134 135 uint drr2; /* data receive register */136 uint drr1;137 uint dxr2; /* data transmit register */138 uint dxr1;139 mcbsp; /* mcbspb means mcbsp buffer receive and transmit data */140 141 define mcbsp0 (*(mcbsp *)0x20)142 define mcbsp1 (*(mcbsp *)0x40)143 de

12、fine mcbsp2 (*(mcbsp *)0x30)144 145 /* serial port sub-address and sub-data registers */146 define spsa0 *(vuint *)0x38147 define spsa0_addr 0x38148 define spsd0 *(vuint *)0x39149 define spsd0_addr 0x39150 define spsa1 *(vuint *)0x48151 define spsa1_addr 0x48152 define spsd1 *(vuint *)0x49153 define

13、 spsd1_addr 0x49154 define spsa2 *(vuint *)0x34155 define spsa2_addr 0x34156 define spsd2 *(vuint *)0x35157 define spsd2_addr 0x35 158 159 /* define sub-address name of serial port */160 define spcr1 0x00 /* serial port control register */161 define spcr2 0x01162 define rcr1 0x02 /* receive control

14、register */163 define rcr2 0x03 164 define xcr1 0x04 /* transmit control register */165 define xcr2 0x05 166 define srgr1 0x06 /* sample rate generator register */167 define srgr2 0x07168 define mcr1 0x08 /* multichannel register */169 define mcr2 0x09 170 define rcera 0x0a /* receive channel enable

15、 register partition a */171 define rcerb 0x0b /* receive channel enable register partition b */172 define xcera 0x0c /* transmit channel enable register partition a */173 define xcerb 0x0d /* transmit channel enable register partition b */174 define pcr 0x0e /* pin control register */175 176 /* cloc

16、k mode register */177 define clkmd *(vuint *)0x58178 179 /* dma channel priority and enable control register */180 define dmprec *(vuint *)0x54 181 182 /* dma channel sub-address register */183 define dmsa *(vuint *)0x55184 185 /* dma data_initiate registers */186 define dmsd1 *(vuint *)0x56187 defi

17、ne dmsd2 *(vuint *)0x57188 189 /* define sub-address name of dma */190 define dmsrc0 0x00 /* dma channel 0 source address register */191 define dmdst0 0x01 /* dma channel 0 destination address register */192 define dmctr0 0x02 /* dma channel 0 element count register */193 define dmsfc0 0x03 /* dma c

18、hannel 0 select and frame count register */194 define dmmcr0 0x04 /* dma channel 0 transfer mode control register */195 define dmsrc1 0x05 /* dma channel 1 source address register */196 define dmdst1 0x06 /* dma channel 1 destination address register */197 define dmctr1 0x07 /* dma channel 1 element

19、 count register */198 define dmsfc1 0x08 /* dma channel 1 sync select and frame count register */199 define dmmcr1 0x09 /* dma channel 1 transfer mode control register */200 define dmsrc2 0x0a /* dma channel 2 source address register */201 define dmdst2 0x0b /* dma channel 2 destination address regi

20、ster */202 define dmctr2 0x0c /* dma channel 2 element count register */203 define dmsfc2 0x0d /* dma channel 2 sync select and frame count register */204 define dmmcr2 0x0e /* dma channel 2 transfer mode control register */205 define dmsrc3 0x0f /* dma channel 3 source address register */206 define

21、 dmdst3 0x10 /* dma channel 3 destination address register */207 define dmctr3 0x11 /* dma channel 3 element count register */208 define dmsfc3 0x12 /* dma channel 3 sync select and frame count register */209 define dmmcr3 0x13 /* dma channel 3 transfer mode control register */210 define dmsrc4 0x14

22、 /* dma channel 4 source address register */211 define dmdst4 0x15 /* dma channel 4 destination address register */212 define dmctr4 0x16 /* dma channel 4 element count register */213 define dmsfc4 0x17 /* dma channel 4 sync select and frame count register */214 define dmmcr4 0x18 /* dma channel 4 t

23、ransfer mode control register */215 define dmsrc5 0x19 /* dma channel 5 source address register */216 define dmdst5 0x1a /* dma channel 5 destination address register */217 define dmctr5 0x1b /* dma channel 5 element count register */218 define dmsfc5 0x1c /* dma channel 5 sync select and frame coun

24、t register */219 define dmmcr5 0x1d /* dma channel 5 transfer mode control register */220 define dmsrcp 0x1e /* dma source program page address (common channel) */221 define dmdstp 0x1f /* dma destination program page address (common channel) */222 define dmidx0 0x20 /* dma element index address reg

25、ister 0 */223 define dmidx1 0x21 /* dma element index address register 1 */224 define dmfri0 0x22 /* dma frame index register 0 */225 define dmfri1 0x23 /* dma frame index register 1 */226 define dmgsa 0x24 /* dma global source address reload register */227 define dmgda 0x25 /* dma global destinatio

26、n address reload register */228 define dmgcr 0x26 /* dma global count reload register */229 define dmgfr 0x27 /* dma global frame count reload register */230 231 /* disable and enable interrupt */232 define int_disable asm(" ssbx intm ")233 define int_enable asm(" rsbx intm ")234

27、 235 /* set and clear intm flag */236 define set_intm asm(" ssbx intm ")237 define clear_intm asm(" rsbx intm ")238 239 /* clear ova ovb flag */240 define clear_ova asm(" rsbx ova ")241 define clear_ovb asm(" rsbx ovb ")242 243 /* set and clear xf flag */244 d

28、efine set_xf asm(" ssbx xf ")245 define clear_xf asm(" rsbx xf ")246 247 /* set and clear ovm flag */248 define set_ovm asm(" ssbx ovm ")249 define clear_ovm asm(" rsbx ovm ")250 251 /* set and clear sxm flag */252 define set_sxm asm(" ssbx sxm ")253 define clear_sxm asm(" rsbx sxm ")254 255 /* set and clear c16 flag */256 define set_c16 asm(" ssbx c16 ")257 define clear_c16 asm(" rsbx c16 ")258 259 /* set and clear ovm fla