数字逻辑原理与实践3-2

1、1 1REVIEW OF LAST CLASS 2 2VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter常闭常闭常开常开常闭常开inP P 沟道沟道NN沟道沟道3 3VCCAZVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gateCMOS 2-input NAND gateQ2CMOS inverter4 43.4 Electrical Behavior of CMOS 3.4 Electrical Behavior of CMOS CircuitsCircuits (CMOS(CMOS电路的电气特性电路的电气特性) )Logic v

2、oltage levels. ( 逻辑电压电平逻辑电压电平)DC noise margins(直流噪声容限直流噪声容限)Fanout.(扇出扇出)Speed, Power consumption(速度、功耗速度、功耗)Noise, Electrostatic discharge(噪声、静电放电噪声、静电放电)Open-drain outputs. Three-state outputs (漏极开路输出、三态输出漏极开路输出、三态输出)5 53.5.1 Logic Levels and Noise Margins 逻辑电平和噪声容限逻辑电平和噪声容限VDD = +5.0VVOUTVINTpTn0

3、 1 016 6CMOS逻辑系列（逻辑系列（HC）电平规格）电平规格高态高态不正常状态不正常状态低态低态VOLmaxVILmaxVIHminVOHminVCC0.1V地地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc07 7直流噪声容限直流噪声容限（DC noise marginDC noise margin）多大的噪声会使最坏输出电压被破坏得不可被输入多大的噪声会使最坏输出电压被破坏得不可被

4、输入端识别端识别.高态高态不正常状态不正常状态低态低态VOLmax=0.1VVILmax=1.35VVIHmin=3.15VVOHmin=4.4V30%VCC the LOW-state DC noise margin is 1.25 V =1.35-0.1(V)The HIGH state DC noise margin. Is 1.25 V=4.4-3.15(V) .8 89 93.5.2 Circuit Behavior with Resistive Loads (带电阻性负载的电路特性带电阻性负载的电路特性)(P103)10103.5.2 Circuit Behavior with R

5、esistive 3.5.2 Circuit Behavior with Resistive Loads(Loads(带电阻性负载的电路特性带电阻性负载的电路特性)(P103)(P103)要求有一定的驱动电流才能工作要求有一定的驱动电流才能工作VCCAZVCCRThevRpRnVThev +VOUTVINaThvenin equivalent network11 11REMEMBERING THVENIN REMEMBERING THVENIN Any two-terminal circuit consisting of only voltage sources and resistors c

6、an be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single resistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thvenin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit.1212Ex

7、ample 1 (P104)Example 1 (P104)1313Resistive model for CMOS LOW outputResistive model for CMOS LOW outputwith resistive load.with resistive load.1414Resistive model for CMOS HIGH outputResistive model for CMOS HIGH outputwith resistive load.with resistive load.1515VOLmaxIOLmax输出为低态时输出为低态时 VOUT 1M Rn电

8、阻性电阻性负载负载100 Sinking current吸收电流吸收电流1616VOHminIOHmax输出为高态时输出为高态时 VOUT = VOHmin输出端提供电流输出端提供电流 sourcing current能提供的最大电流能提供的最大电流 IOHmax （拉电流）（拉电流）VCC = + 5.0VRpRn1M 电阻性电阻性负载负载200 Sourcing current 提供电流提供电流1717VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0输出为低态时，输出为低态时，估计吸

9、收电流：估计吸收电流：ThevThevOUTRVI输出为高态时，输出为高态时，估计提供电流：估计提供电流：ThevThevCCOUTRVVI1818EXAMPLE 2 (P107)EXAMPLE 2 (P107)19193.5.3 Circuit Behavior with Nonideal Inputs (P108)20203.5.3 Circuit Behavior with Nonideal 3.5.3 Circuit Behavior with Nonideal InputsInputs非理想输入时的电路特性非理想输入时的电路特性VCC = + 5.0V400 2.5k VIN 1.5

10、VVOUT 4.31VVCC = + 5.0V4k 200 VIN 3.5VVOUT 0.24V输出电压变坏（有电阻性负载时更差）输出电压变坏（有电阻性负载时更差）更糟糕的是：更糟糕的是：Iwasted ， Pwasted 2121Example 3 (P110)Example 3 (P110)22223.5.4 Fanout(P111)23233.5.4 Fanout 3.5.4 Fanout （扇出（扇出）The fanout of a logic gate is the number of inputs that the gate can drive without exceeding

11、its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW. 在不超出其最坏情况负载规格的条件下，在不超出其最坏情况负载规格的条件下， 一个逻辑门能驱动的输入端个数。一个逻辑门能驱动的输入端个数。扇出需考虑输出高电平和低电平

12、两种状态扇出需考虑输出高电平和低电平两种状态 总扇出总扇出minmin（高态扇出，低态扇出）高态扇出，低态扇出）直流扇出直流扇出 和和 交流扇出交流扇出2424EXAMPLE 3 (P111)EXAMPLE 3 (P111) IImax for an HC-series CMOS input in any state is 1 A .The LOW-state fanout for an HC-series output driving HC-series inputs is 20. IImax for an HC-series CMOS input in any state is 1 A .

13、The HIGH-state fanout for an HC-series output driving HC-series inputs is 20.2525EXAMPLE 4EXAMPLE 4CMOS(TTLoutput level)CMOSCMOS the fanout of an HC-series output driving HC-series inputs at TTLlevels is 4000.直流扇出直流扇出26263.5.5 Effects of Loading(3.5.5 Effects of Loading(负载效应负载效应) ) 输出负载大于它的扇出能力时（输出负

14、载大于它的扇出能力时（P111） In the LOW state, the output voltage (VOL) may increase beyond VOLmax.In the HIGH state, the output voltage (VOH) may fall below VOHmin.输出电压变差输出电压变差Propagation delay to the output may increase beyond specifications. Output rise and fall times may increase beyond their specifications

15、.传输延迟和转换时间变长传输延迟和转换时间变长 The operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure. 温度可能升高，可靠性降低，器件失效温度可能升高，可靠性降低，器件失效.27273.5.6 Unused Inputs(3.5.6 Unused Inputs(不用的不用的CMOSCMOS输入端输入端) )不用的不用的CMOS输入端绝对不能悬空输入端绝对不能悬空XZ1k +

16、5VXZ增加了驱动信号的电容负增加了驱动信号的电容负载，使操作变慢载，使操作变慢XZ1k1k 28283.6 CMOS Dynamic Electrical Behavior(P114)29293.6 CMOS Dynamic Electrical Behavior3.6 CMOS Dynamic Electrical Behavior CMOSCMOS动态电气特性动态电气特性考虑两个方面：考虑两个方面：速度速度功耗功耗转换时间（转换时间（transition time）传播延迟（传播延迟（propagation delay）静态功耗（静态功耗（static power dissipation

17、）动态功耗（动态功耗（dynamic power dissipation）30303.6 CMOS Dynamic Electrical 3.6 CMOS Dynamic Electrical BehaviorBehavior (CMOS(CMOS动态电气特性动态电气特性) ) CMOS器件的速度和功耗在很大程度器件的速度和功耗在很大程度上取决于器件及其负载的动态特性。上取决于器件及其负载的动态特性。速度取决于两个特性：速度取决于两个特性：transition time（转换时间（转换时间）propagation delay（传播延迟（传播延迟）逻辑电路的输出从一种状态变为另一种状态所需的时间

18、逻辑电路的输出从一种状态变为另一种状态所需的时间从输入信号变化到产生输出信号变化所需的时间从输入信号变化到产生输出信号变化所需的时间31313.6.1 Transition Time3.6.1 Transition Time ( (转换时间转换时间) ) rise time(上升时间上升时间) ) t tr r fall time(下降时间下降时间) ) t tf f the “on” transistor resistance(晶体管的晶体管的“导通导通”电阻电阻)stray capacitance(寄生电容寄生电容)VCC = + 5.0VRLRpRnVL+CL电容两端电压不能突变电容两端

19、电压不能突变在实际电路中在实际电路中可用时间常数可用时间常数近似转换时间近似转换时间P115 Figure 3-363232Example 4 (P117)Example 4 (P117)estimates of 10 ns for fall time .3333EXAMPLE 5 (P117)EXAMPLE 5 (P117)estimates of 20 ns for rise time .34343.6.2 Propagation Delay(3.6.2 Propagation Delay(传播延迟传播延迟) )P83 图图3-42VINVOUTLHtPHLtP信号通路：一个特定输入信号到逻辑元件的信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。特定输出信号所经历的电气通路。35353.6.2 Propagation Delay(3.6.2 Propagation Delay(传播延迟传播延迟