EDA技术及应用项目教程 项目6 参考答案

项目6参考答案1.FPGA的端口外接8只发光二极管(D0~D7)，要求编写VerilogHDL程序实现发光二极管的拉幕式与闭幕式显示控制。分析：所谓拉幕式是指从中间往两端逐个点亮，即首先D3、D4亮，再D2~D5点亮，接着D1~D6点亮，最后D0~D7全部点亮；闭幕式是指从两端往中间逐个熄灭，即首先D0、D7熄灭，再D0、D1、D6、D7熄灭，接着D0~D2、D5~D7熄灭，最后D0~D7全部熄灭。此例可由顶层文件ex_LED1.v、分频模块文件freq.v和显示控制模块文件LED_Display.v构成，参考代码如下：//分频模块文件freq.vmodulefreq(clkin,clkout);parametern=50_000_000;//parametern=10;inputclkin;outputregclkout;reg[24:0]cnt;always@(posedgeclkin) if(cnt==(n/2-1))begin cnt<=1'b0;clkout<=~clkout;end else cnt<=cnt+1'b1;endmodule//显示控制模块文件LED_Display.vmoduleLED_Display(clk,pause,rst,LED);inputclk,pause,rst;outputreg[7:0]LED;parameterst0=4'b0000,st1=4'b0001,st2=4'b0010;parameterst3=4'b0011,st4=4'b0100,st5=4'b0101;parameterst6=4'b0110,st7=4'b0111;reg[3:0]current_state,next_state;//定义现态和次态always@(posedgeclk,negedgerst)begin if(!rst)current_state<=st0; elsecurrent_state<=next_state; endalways@(pause,current_state)begin case(current_state) st0:begin LED<=8'b0001_1000; if(pause==0)next_state<=st0; elsenext_state<=st1; end st1:begin LED<=8'b0011_1100; if(pause==0)next_state<=st1; elsenext_state<=st2; end st2:begin LED<=8'b0111_1110; if(pause==0)next_state<=st2; elsenext_state<=st3; end st3:begin LED<=8'b1111_1111; if(pause==0)next_state<=st3; elsenext_state<=st4; end st4:begin LED<=8'b0111_1110; if(pause==0)next_state<=st4; elsenext_state<=st5; end st5:begin LED<=8'b0011_1100; if(pause==0)next_state<=st5; elsenext_state<=st6; end st6:begin LED<=8'b0001_1000; if(pause==0)next_state<=st6; elsenext_state<=st7; end st7:begin LED<=8'b0000_0000; if(pause==0)next_state<=st7; elsenext_state<=st0; end defaultnext_state<=st0; endcaseendendmodule//顶层文件ex_LED1.vmoduleex_LED1(clk_sys,pause,rst,LED);inputclk_sys,pause,rst;output[7:0]LED;wireclk_new;freqU1(.clkin(clk_sys),.clkout(clk_new));LED_DisplayU2(.clk(clk_new),.pause(pause),.rst(rst),.LED(LED));endmodule2.FPGA的端口外接8只发光二极管(D0~D7)，要求编写VerilogHDL程序实现发光二极管的复杂广告灯显示控制。其显示规律为：正向流水→反向流水→隔灯闪烁3次→高四盏、低四盏闪烁2次→隔两盏闪烁3次，再重复循环。分析：此例可由顶层文件ex_LED2.v、分频模块文件freq.v和显示控制模块文件LED_Display.v构成，参考代码如下：//分频模块文件freq.vmodulefreq(clkin,clkout);parametern=50_000_000;//parametern=10;inputclkin;outputregclkout;reg[24:0]cnt;always@(posedgeclkin) if(cnt==(n/2-1))begin cnt<=1'b0;clkout<=~clkout;end else cnt<=cnt+1'b1;endmodule//显示控制模块文件LED_Display.vmoduleLED_Display(clk,pause,rst,LED);inputclk,pause,rst;outputreg[7:0]LED;parameterst0=5'b00000,st1=5'b00001,st2=5'b00010;parameterst3=5'b00011,st4=5'b00100,st5=5'b00101;parameterst6=5'b00110,st7=5'b00111,st8=5'b01000;parameterst9=5'b01001,st10=5'b01010,st11=5'b01011;parameterst12=5'b01100,st13=5'b01101,st14=5'b01110;parameterst15=5'b01111,st16=5'b10000,st17=5'b10001;parameterst18=5'b10010,st19=5'b10011,st20=5'b10100;parameterst21=5'b10101,st22=5'b10110,st23=5'b10111;parameterst24=5'b11000,st25=5'b11001,st26=5'b11010;parameterst27=5'b11011,st28=5'b11100,st29=5'b11101;parameterst30=5'b11110;reg[4:0]current_state,next_state;//定义现态和次态always@(posedgeclk,negedgerst)begin if(!rst)current_state<=st0; elsecurrent_state<=next_state; endalways@(pause,current_state)begin case(current_state) st0:begin LED<=8'b0000_0001; if(pause==0)next_state<=st0; elsenext_state<=st1; end st1:begin LED<=8'b0000_0010; if(pause==0)next_state<=st1; elsenext_state<=st2; end st2:begin LED<=8'b0000_0100; if(pause==0)next_state<=st2; elsenext_state<=st3; end st3:begin LED<=8'b0000_1000; if(pause==0)next_state<=st3; elsenext_state<=st4; end st4:begin LED<=8'b0001_0000; if(pause==0)next_state<=st4; elsenext_state<=st5; end st5:begin LED<=8'b0010_0000; if(pause==0)next_state<=st5; elsenext_state<=st6; end st6:begin LED<=8'b0100_0000; if(pause==0)next_state<=st6; elsenext_state<=st7; end st7:begin LED<=8'b1000_0000; if(pause==0)next_state<=st7; elsenext_state<=st8; end st8:begin LED<=8'b0100_0000; if(pause==0)next_state<=st8; elsenext_state<=st9; end st9:begin LED<=8'b0010_0000; if(pause==0)next_state<=st9; elsenext_state<=st10; end st10:begin LED<=8'b0001_0000; if(pause==0)next_state<=st10; elsenext_state<=st11; end st11:begin LED<=8'b0000_1000; if(pause==0)next_state<=st11; elsenext_state<=st12; end st12:begin LED<=8'b0000_0100; if(pause==0)next_state<=st12; elsenext_state<=st13; end st13:begin LED<=8'b0000_0010; if(pause==0)next_state<=st13; elsenext_state<=st14; end st14:begin LED<=8'b0000_0001; if(pause==0)next_state<=st14; elsenext_state<=st15; end st15:begin LED<=8'b1010_1010; if(pause==0)next_state<=st15; elsenext_state<=st16; end st16:begin LED<=8'b0101_0101; if(pause==0)next_state<=st16; elsenext_state<=st17; end st17:begin LED<=8'b1010_1010; if(pause==0)next_state<=st17; elsenext_state<=st18; end st18:begin LED<=8'b0101_0101; if(pause==0)next_state<=st18; elsenext_state<=st19; end st19:begin LED<=8'b1010_1010; if(pause==0)next_state<=st19; elsenext_state<=st20; end st20:begin LED<=8'b0101_0101; if(pause==0)next_state<=st20; elsenext_state<=st21; end st21:begin LED<=8'b1111_0000; if(pause==0)next_state<=st21; elsenext_state<=st22; end st22:begin LED<=8'b0000_1111; if(pause==0)next_state<=st22; elsenext_state<=st23; end st23:begin LED<=8'b1111_0000; if(pause==0)next_state<=st23; elsenext_state<=st24; end st24:begin LED<=8'b0000_1111; if(pause==0)next_state<=st24; elsenext_state<=st25; end st25:begin LED<=8'b1100_1100; if(pause==0)next_state<=st25; elsenext_state<=st26; end st26:begin LED<=8'b0011_0011; if(pause==0)next_state<=st26; elsenext_state<=st27; end st27:begin LED<=8'b1100_1100; if(pause==0)next_state<=st27; elsenext_state<=st28; end st28:begin LED<=8'b0011_0011; if(pause==0)next_state<=st28; elsenext_state<=st29; end st29:begin LED<=8'b1100_1100; if(pause==0)next_state<=st29; elsenext_state<=st30; end st30:begin LED<=8'b0011_0011; if(pause==0)next_state<=st30; elsenext_state<=st0; enddefaultnext_state<=st0; endcaseendendmodule//顶层文件ex_LED2.vmoduleex_LED2(clk_sys,pause,rst,LED);inputclk_sys,pause,rst;output[7:0]LED;wireclk_new;freqU1(.clkin(clk_sys),.clkout(clk_new));LED_DisplayU2(.clk(clk_new),.pause(pause),.rst(rst),.LED(LED));endmodule3.FPGA外接8位共阴极LED数码管，编写VerilogHDL程序使数码管显示“872AF635”。分析：8位共阴极LED数码管采用动态显示，需要对50MHz的频率进行分频，所以此例可由顶层文件LED_Display.v、分频模块文件freq.v和LED动态显示模块文件Display.v构成，参考代码如下：//分频模块文件freq.vmodulefreq(clkin,clk_1kHz);parametercnt_1kHz=50_000;//1kHz分频系数inputclkin;outputregclk_1kHz;reg[15:0]cnt;always@(posedgeclkin)//1kHz频率 if(cnt==(cnt_1kHz/2-1))begin cnt<=1'b0;clk_1kHz<=~clk_1kHz;end else cnt<=cnt+1'b1;endmodule//LED动态显示模块文件Display.v//8位LED数码管动态显示moduleDisplay(clk,sel,seg_out);inputclk;outputreg[2:0]sel;outputreg[7:0]seg_out;reg[3:0]num_in;reg[31:0]Din={4'd8,4'd7,4'd2,4'd10,4'd15,4'd6,4'd3,4'd5};always@(posedgeclk)begin if(sel==3'd7) sel<=0; else sel=sel+1'b1; endalways@(sel)begin case(sel) 3'd0:num_in=Din[3:0]; 3'd1:num_in=Din[7:4]; 3'd2:num_in=Din[11:8]; 3'd3:num_in=Din[15:12]; 3'd4:num_in=Din[19:16]; 3'd5:num_in=Din[23:20]; 3'd6:num_in=Din[27:24]; 3'd7:num_in=Din[31:28]; endcaseendalways@(num_in)begin case(num_in) 4'b0000:seg_out=8'h3F;//显示0 4'b0001:seg_out=8'h06;//显示1 4'b0010:seg_out=8'h5B;//显示2 4'b0011:seg_out=8'h4F;//显示3 4'b0100:seg_out=8'h66;//显示4 4'b0101:seg_out=8'h6D;//显示5 4'b0110:seg_out=8'h7D;//显示6 4'b0111:seg_out=8'h07;//显示7 4'b1000:seg_out=8'h7F;//显示8 4'b1001:seg_out=8'h6F;//显示9 4'b1010:seg_out=8'h77;//显示A 4'b1011:seg_out=8'h7C;//显示B 4'b1100:seg_out=8'h39;//显示C 4'b1101:seg_out=8'h5E;//显示D 4'b1110:seg_out=8'h79;//显示E 4'b1111:seg_out=8'h71;//显示F endcase endendmodule//顶层文件LED_Display.vmoduleLED_Display(clk_sys,cs,LED);inputclk_sys;output[2:0]cs;output[7:0]LED;wireclk_1kHz,clk_2Hz;freqU1(.clkin(clk_sys),.clk_1kHz(clk_1kHz));DisplayU2(.clk(clk_1kHz),.sel(cs),.seg_out(LED));endmodule4.FPGA外接8位共阴极LED数码管，编写VerilogHDL程序，要求每按一次K1按钮，数码管显示的内容加1；每按一次K2按钮，数码管显示的内容减1。分析：可参考学习工作页-任务2.5分频器的设计-偶数分频器的应用5.FPGA外接蜂鸣器，编写VerilogHDL程序，使FPGA产生和输出PWM信号控制蜂鸣器进行七个音调“哆来咪发梭拉西”的循环鸣叫，每个音阶持续鸣叫0.5s后鸣叫下一个音阶。以下为8个按键控制音调输出的参考代码，要实现本例功能则还需要进行0.5s的延时控制，以及每隔0.5s时cnt计1次数，系统根据cnt计数次数选择相应的freq即可。当cnt计数达到8次时，cnt清零为下轮循环鸣叫作准备。//---------------------------------------------------------------------------//-- 描述 : 用按键可以弹奏do,re,mi,fa,so,la,si,do//---------------------------------------------------------------------------modulebuzzer( //输入端口 CLK_50M,RST_N,KEY, //输出端口 LED,Buzzer);//---------------------------------------------------------------------------//-- 外部端口声明//---------------------------------------------------------------------------input CLK_50M; //时钟的端口,开发板用的50MHz晶振input RST_N; //复位的端口,低电平复位input [7:0] KEY; //按键端口output LED; //LED灯端口output Buzzer; //蜂鸣器端口//---------------------------------------------------------------------------//-- 内部端口声明//---------------------------------------------------------------------------reg [15:0] time_cnt; //用来控制蜂鸣器发声频率的定时计数器reg [15:0] time_cnt_n; //time_cnt的下一个状态reg [15:0] freq; //各种音调的分频值reg Buzzer_reg; //用来控制蜂鸣器发声的寄存器reg Buzzer_reg_n; //Buzzer_reg的下一个状态//---------------------------------------------------------------------------//-- 逻辑功能实现 //---------------------------------------------------------------------------//时序电路,用来给time_cnt寄存器赋值always@(posedgeCLK_50MornegedgeRST_N)begin if(!RST_N) //判断复位 time_cnt<=16'b0; //初始化time_cnt值 else time_cnt<=time_cnt_n; //用来给time_cnt赋值end//组合电路,判断频率,让定时器累加always@(*)begin if(time_cnt==freq) //判断分频值 time_cnt_n=16'b0; //定时器清零操作 else time_cnt_n=time_cnt+1'b1; //定时器累加操作end//时序电路,用来给Buzzer_reg寄存器赋值always@(posedgeCLK_50MornegedgeRST_N)begin if(!RST_N) //判断复位 Buzzer_reg<=1'b0; //初始化Buzzer_reg值 else Buzzer_reg<=Buzzer_reg_n; //用来给Buzzer_reg赋值end//组合电路,判断频率,使蜂鸣器发声always@(*)begin if(!freq) Buzzer_reg_n=0; else begin if(time_cnt==freq) //判断分频值 Buzzer_reg_n=~Buzzer_reg; //改变蜂鸣器的状态 else Buzzer_reg_n=Buzzer_reg; //蜂鸣器的状态保持不变 end end//组合电路,按键选择分频值来实现蜂鸣器发出不同声音//中音do的频率为523.3hz，freq=50*10^6/(523*2)=47774always@(*)begin case(KEY) 8'b11111110:freq=16'd47774; //中音1的频率值523.3Hz 8'b11111101:freq=16'd42568; //中音2的频率值587.3Hz 8'b11111011:freq=16'd37919; //中音3的频率值659.3Hz 8'b11110111:freq=16'd35791; //中音4的频率值698.5Hz 8'b11101111:freq=16'd31888; //中音5的频率值784Hz 8'b11011111:freq=16'd28409; //中音6的频率值880Hz 8'b10111111:freq=16'd25309; //中音7的频率值987.8Hz 8'b01111111:freq=16'd23889; //高音1的频率值1046.5Hz default :freq=16'd0; endcaseendassignBuzzer=Buzzer_reg; //最后,将寄存器的值赋值给端口BuzzerassignLED=Buzzer_reg; //LED作指示灯endmodule6.编写VerilogHDL程序，设计一个基于FPGA的序列检测器。分析：序列检测器在很多数字系统中都不可缺少，有其是在通信系统当中。序列检测器的作用就是从一系列的码流中找出用户希望出现的序列，序列可长可段。比如在通信系统中，数据流帧头的检测就属于一个序列检测器。序列检测器的类型有很多种，有逐比特比较的，有逐字节比较的，也有其他的比较方式，实际应用中需要采用何种比较方式，主要是看序列的多少以及系统的延时要求。现在就逐比特比较的原理简单的介绍一下。逐比特比较的序列检测器是在输入一个特定波特率的二进制码流中，每进一个二进制码，预期望的序列相比较。首先比较第一个码，如果第一个码与期望的序列的第一个码相同，那么下一个进来的二进制码再和期望的序列的第二个码相比较，依次比较下去，直到所有的码都和期望的序列相一致，就认为检测到一个期望的序列。如果检测过程中出现一个码与期望的序列当中对应的码不一样，则从头开始比较。modulecheck(clk,RSTn,seq,key,s,digseg,led,Error_Num); inputclk;//系统时钟 inputRSTn;//系统复位 input[7:0]seq;//被检测的8位序列 inputkey;//按键启动检测10100101 outputled;//如果检测到10100101，则LED灯亮，否则灭 output[2:0]s; output[7:0]digseg; outputreg[3:0]Error_Num; reg[3:0]err; reg[7:0]seq_reg; regkey_flag; regled_flag; reg[15:0]count; regclk1kHz; reg[7:0]state; reg[3:0]count_flag; regA; //产生1Khz频率 parameterF1kHz=15'd25_000; always@(posedgeclkornegedgeRSTn) if(!RSTn) count<=15'd0; elseif(count==F1kHz) begin count<=15'd0; clk1kHz<=~clk1kHz; end else count<=count+1'b1; //状态机的状态编号 parameterstart=8'b0000_0000; parameterstatus1=8'b0000_0001; parameterstatus2=8'b0000_0010; parameterstatus3=8'b0000_0100; parameterstatus4=8'b0000_1000; parameterstatus5=8'b0001_0000; parameterstatus6=8'b0010_0000; parameterstatus7=8'b0100_0000; parameterstatus8=8'b1000_0000;//如果检测到10100101，则按下检测启动键（PIN_71），LED灯亮，其余灯灭 always@(posedgeclk1kHz) begin if(!RSTn) begin state<=start; key_flag<=1'b0; count_flag<=3'd0; end elseif(!key) begin seq_reg<=seq; state<=start; count_flag<=3'd0; key_flag<=1'b1; end else begin if(count_flag>3'b111) begin key_flag<=1'b0; end elseif(key_flag) begin A<=(seq_reg>>count_flag)&8'b0000_0001;//000 case(state) start: if(A)//1 begin count_flag<=count_flag+1'b1;//001 state<=status1; end else begin count_flag<=count_flag+1'b1; state<=start; end status1:if(!A)//0 begin count_flag<=count_flag+1'b1;//010 state<=status2; end else begin count_flag<=count_flag+1'b1; state<=status1; end status2:if(A)//1 begin count_flag<=count_flag+1'b1;//011 state<=status3; end else begin count_flag<=count_flag+1'b1; state<=start; end status3:if(!A)//0 begin count_flag<=count_flag+1'b1;//100 state<=status4; end else begin count_flag<=count_flag+1'b1; state<=status1; end status4: