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设计文挡 唐老师，你好！由于我的疏忽，没有能把正确的原文件传给你，不好意思哈，最近是焦头烂额呀！：）现在我把我的设计文档给您，请你指正，谢谢！module converter(binary,q);input 3:0 binary;output7:0 q;reg c_0;reg3:0 sum,s;wire 3:0 binary;reg 7:0 q;reg 7:0 j1;parameter gate=0101,just=0011;initial begin c_0=0; end leftshift f1(q7:0,j17:0,binary3:0);comp_4 c1(gt,lt,q3:0,gate);fa a1(sum,q3:0,just,out_c,c_o);always(binary) begin if (gt0) begin q0=sum0; q1=sum1; q2=sum2; q3=sum3; end end d_latch_gates m6(q3,s3,q2); d_latch_gates m7(q2,s2,q1); d_latch_gates m8(q1,s1,q0); d_latch_gates m9(q0,s0,binary0); endmodule module d_latch_gates(s,s_bar,p);input p;output s,s_bar;wire not_s;not(not_s,s);nor #1 m1(s_bar,s,p);nor #1 m2(s,s_bar,not_s);endmodulemodule comp_4(gt,lt,a,b);/comparerinput 3:0 a,b;output gt,lt;reg gt,lt;always(a or b)begin if (ab) begin gt=1;lt=0; end else if(ab) begin gt=0;lt=1; end else begin gt=0;lt=0; endendendmodule module leftshift(t,s,d);/leftshiftinput 3:0 d;output 3:0 t,s;reg 1:0 state; d_latch_gates n0(t0,s0,d3); d_latch_gates n1(t1,s1,t0); d_latch_gates n2(t0,s0,d2); d_latch_gates n3(t2,s2,t1); d_latch_gates n4(t1,s1,t0); d_latch_gates n5(t0,s0,d1); endmodule module full_adder_gate(sum,c_out,x,y,c_in);/full_adder input x,y,c_in; output sum,c_out; wire w1,w2,w3; xor(w1,x,y), (sum,w1,c_in); and( w2,x,y), (w3,w1,c_in); or(c_out,w2,w3); endmodule module fa(sum,m,just,out_c,c_0);/sum input3:0 m,c_0,just; output3:0 sum ; output out_c; wire c_1,c_2,c_3; full_adder_gate z1(sum0,c_1,m0,just0,c_0); full_adder_gate z2(sum1,c_2,m1,just1,c_1); full_adder_gate z3(sum2,c_3,m2,just2,c_2); full_adder_gate z4(sum3,out_c,m3,just3,c_3); endmoduletimescale 10ms/1ms module test_converter; reg 3:0 binary; wire 7:0 q; initial begin