Design Verification with SignalTapII(stp_final_4_1).ppt

1、FAE Training MaterialQuartus II Version 4.1,Design Verification with SignalTap II,2,Agenda,Using SignalTap II,New Feature Update,Applications of New Features,3,The “Logic Analyzer” in Your FPGA,Soft IP is Added to Your Design to Emulate an External Logic Analyzer,Logic Analyzer Integration is Handle

2、d by the Quartus II Fitter Seamlessly Capture Signals in Real-Time Through the JTAG Interface,4,Using SignalTap II,Enable the Analyzer in Quartus II & Compile,Capture Signals & Analyze Data,Setup the Logic Analyzer,Build Triggers Set Sample Depth Add Data Signals Add Trigger Signals Add Sample Clock

3、,Instantiate Analyzer in HDL Placement & Routing of Analyzer using Quartus II,Time Bars Export File Data Log,5,Agenda,Using SignalTap II,New Feature Update,Applications of New Features,6,SignalTap II HDL Instantiation,Instantiate SignalTap II Instance Directly in Your HDL In Quartus II v4.0 SignalTa

4、p II was Automatically Integrated with Your Design Use the MegaWizard to Create Custom Configuration,7,SignalTap II HDL Flow,Build MegaWizard Output,8,SignalTap II HDL Flow (contd),2. Instantiate and Connect MegaWizard Output in HDL The Signals Must Be Visible in the Module You Are Tapping,Module A,

5、Module B,signal foo1,signal foo2,signal foo3,signal foo4,STP Instance,data_in 0.n,signal oof2,signal oof1,signal oof3,Internal Signals from Module B Must be Connected to Ports in Module B in Order for Them to be Visible to the STP Module,9,SignalTap II HDL Flow (contd),3. Compile Design In Quartus I

6、I Examine the SignalTap II Section of the Compilation Report 4. Automatically Generate an STP file Based on the MegaWizard Output Select Create SignalTap II File From Design Instance (File Create Menu) To Allow You To Store Captured Data,10,HDL Advantages/Disadvantages,Design File Management is Made

7、 Easier No STP File to Add to Projects You Have to Instantiate STP at the Hierarchical Boundary Where the Signals that you want to Tap are,11,Counter Construct: Introduction,Customer Problem: How Do I Trigger on an Event that Occurs X Number of Times? In Quartus II v4.0: Use Multiple Trigger Levels

8、With the Same Expression Repeated for Each Trigger Level Limited to 10 Trigger Levels Tedious In Quartus II v4.1: Build a Trigger Expression That Uses the Counter Construct in the Advanced Trigger Condition Editor,12,Counter Construct : Example,You Can Build a Trigger Condition That Triggers After a

9、n Event Occurs a User Defined Number of Times Triggers When BUS0 & BUS1 are Equivalent 3 Times,13,Counter Construct : Operation Mode,Continuous Mode - The Input to the Event Counter Must be High for the Specified Number of Consecutive Clock Cycles Event Count Mode The Input to the Event Counter Does

10、 not Have to be High for Successive Clock Cycles State Mode - The Internal Counter Increments When There is a Low-to-High Transition on the Input of the Event Counter,14,Counter Construct : Caveats,In a Multi-Level Trigger Environment the Counter Construct Can Only be Used in the First Trigger Level

11、 2. The Counter Construct Cannot be Used in Segmented Acquisition Mode if You Only Have One Trigger Level,15,SOF Manager,Customer Problem: Managing All of the STP Files and Their Associated Programming Files Is Tedious. I dont Know Which STP File Matches up with Which Programming File Using the SOF

12、Manager You Can Embed Multiple SOF into One STP File . Why is this Useful? .,16,Multiple STP Configurations,Using the Data Log Feature in SignalTap II You Can Store More than One Configuration of an Analyzer,Using the SOF Manager You Can Store a SOF for Each Configuration of the Analyzer,17,Using th

13、e SOF Manager,Compile Your Design w/ STP Configuration 1 Attach the SOF That is Generated with Configuration 1 to the STP File,18,Using the SOF Manager (contd),2. Create Your New STP Configuration 3. Select to Create a New Signal Set 4. Compile Your Design w/ the New Configuration,19,Using the SOF M

14、anager (contd),5. Attach the SOF to the STP File 6. Toggle Between STP Configurations by Double Clicking in the Data Log The SOFs Listed in the SOF Manager Will Automatically Display Which SOF is Compatible with the Active Configuration,20,Standalone SignalTap II,You can Install a “Lite” Version of

15、SignalTap II in the Lab to Debug a Design PC Only Only 15MB Install Files Suitable for Lower-End Machines Found in a Lab Small Differences Between Full and Lite Versions Nodes and Instances Cannot be Added or Deleted Advanced Trigger Equations Cannot be Modified,21,Standalone Installation,The Quartu

16、s II Stand-Alone Programmer Contains the Files for the Standalone Version of SignalTap II,22,Agenda,Using the Chip Editor,New Feature Update,Applications of New Features,23,Remote Debugging w/ SignalTap II,SignalTap II Can be Used to Debug a Design that is Running on a PCB in a Remote Location,24,1.

17、 Setting Up The Remote Machine,Install Standalone Version of the Quartus II Programmer Setup the JTAG Server,25,2. Setting Up The Local Machine,Add the JTAG Server That Was Created on the Remote Machine to the Local Machine,26,3. Putting It All Together,Select the Hardware on the Remote Machine and Start SignalTap II,27,Summary,Significant Increase in User B