资源目录
压缩包内文档预览：
编号：49592532
类型：共享资源
大小：6.25MB
格式：RAR
上传时间：2020-02-15
上传人：闰***
认证信息
个人认证
冯**（实名认证）
河南
IP属地：河南
15
积分
- 关 键 词：
-
025
数字
示波器
制作
- 资源描述：
-
025、数字示波器的制作,025,数字,示波器,制作
- 内容简介：
-
TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20031POST OFFICE BOX 655303 DALLAS, TEXAS 75265features?Analog Input Range TLC5510 . . . 2 V Full Scale TLC5510A . . . 4 V Full Scale?8-Bit Resolution?Integral Linearity Error0.75 LSB Max (25C)1 LSB Max (20C to 75C)?Differential Linearity Error0.5 LSB Max (25C)0.75 LSB Max (20C to 75C)?Maximum Conversion Rate20 Mega-Samples per Second(MSPS) Max?5-V Single-Supply Operation?Low Power ConsumptionTLC5510 . . . 127.5 mW TypTLC5510A . . . 150 mW Typ(includes reference resistor dissipation)?TLC5510 is Interchangeable With SonyCXD1175applications?Digital TV?Medical Imaging?Video Conferencing?High-Speed Data Conversion?QAM Demodulators descriptionThe TLC5510 and TLC5510A are CMOS, 8-bit, 20MSPS analog-to-digital converters (ADCs) thatutilize a semiflash architecture. The TLC5510 andTLC5510A operate with a single 5-V supply andtypically consume only 130 mW of power.Included is an internal sample-and-hold circuit,parallel outputs with high-impedance mode, andinternal reference resistors.The semiflash architecture reduces powerconsumption and die size compared to flashconverters. By implementing the conversion in a2-step process, the number of comparators issignificantly reduced. The latency of the dataoutput valid is 2.5 clocks.The TLC5510 uses the three internal referenceresistors to create a standard, 2-V, full-scaleconversion range using VDDA. Only external jumpers are required to implement this option and eliminates theneed for external reference resistors. The TLC5510A uses only the center internal resistor section with anexternally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25Cand a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications includea differential gain of 1% and differential phase of 0.7 degrees.The TLC5510 and TLC5510A are characterized for operation from 20C to 75C.AVAILABLE OPTIONSPACKAGEMAXIMUM FULL SCALETATSSOP (PW)SOP (NS)(TAPE AND REEL ONLY)MAXIMUM FULL-SCALEINPUT VOLTAGE20C to 75CTLC5510IPWTLC5510INSLE2 V20C to 75CTLC5510AINSLE4 VPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Copyright 1994 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.123456789101112242322212019181716151413OEDGNDD1(LSB)D2D3D4D5D6D7D8(MSB)VDDDCLKDGNDREFBREFBSAGNDAGNDANALOG INVDDAREFTREFTSVDDAVDDAVDDDPW OR NS PACKAGE(TOP VIEW)Available in tape and reel only and orderedas the shown in the Available Options tablebelow.TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20032POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramLower SamplingComparators(4-Bit)Lower Encoder(4-Bit)Lower DataLatchLower SamplingComparators(4-Bit)Lower Encoder(4-Bit)Upper SamplingComparators(4-Bit)Upper Encoder(4-Bit)Upper DataLatchClockGeneratorOED1(LSB)D2D3D4D5D6D7D8(MSB)CLKREFBREFTREFBSAGNDAGNDANALOG INVDDAREFTS270 NOM80 NOM320 NOMResistorReferenceDividerschematics of inputs and outputsEQUIVALENT OF ANALOG INPUTVDDAAGNDANALOG INEQUIVALENT OF EACH DIGITAL INPUTVDDDDGNDOE, CLKEQUIVALENT OF EACH DIGITAL OUTPUTVDDDDGNDD1D8TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20033POST OFFICE BOX 655303 DALLAS, TEXAS 75265Terminal FunctionsTERMINALI/ODESCRIPTIONNAMENO.I/ODESCRIPTIONAGND20, 21Analog groundANALOG IN19IAnalog inputCLK12IClock inputDGND2, 24Digital groundD1D8310ODigital data out. D1 = LSB, D8 = MSBOE1IOutput enable. When OE = low, data is enabled. When OE = high, D1D8 is in high-impedance state.VDDA14, 15, 18Analog supply voltageVDDD11, 13Digital supply voltageREFB23IReference voltage in bottomREFBS22Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-Vreference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected toground.REFT17IReference voltage in topREFTS16Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-Vreference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected toVDDA.absolute maximum ratingsSupply voltage, VDDA, VDDD 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference voltage input range, VREFT, VREFB AGND to VDDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog input voltage range, VI(ANLG) AGND to VDDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital input voltage range, VI(DGTL) DGND to VDDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital output voltage range, VO(DGTL) DGND to VDDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA 20C to 75C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg 55C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsMINNOMMAXUNITVDDAAGND4.7555.25VSupply voltageVDDDAGND4.7555.25VAGNDDGND1000100mVReference input voltage (top), Vref(T)TLC5510AVREFB+24VReference input voltage (bottom), Vref(B)TLC5510A0VREFT4VAnalog input voltage range, VI(ANLG)VREFBVREFTVHigh-level input voltage, VIH4VLow-level input voltage, VIL1VPulse duration, clock high, tw(H) (see Figure 1)25nsPulse duration, clock low, tw(L) (see Figure 1)25nsThe reference voltage levels for the TLC5510 are derived through an internal resistor divider between VDDA and ground and therefore are notderived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, thereference voltage is externally applied across the center divider resistor.TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20034POST OFFICE BOX 655303 DALLAS, TEXAS 75265electrical characteristics at VDD = 5 V, VREFT = 2.5 V, VREFB = 0.5 V, f(CLK) = 20 MHz, TA = 25C (unlessotherwise noted)digital I/OPARAMETERTEST CONDITIONSMINTYPMAXUNITIIHHigh-level input currentVDD = MAX,VIH = VDD5AIILLow-level input currentVDD = MAX,VIL = 05AIOHHigh-level output currentOE = GND,VDD = MIN,VOH = VDD0.5 V1.5mAIOLLow-level output currentOE = GND,VDD = MIN,VOL = 0.4 V2.5mAIOZHHigh-level high-impedance-stateoutput leakage currentOE = VDD,VDD = MAXVOH = VDD16AIOZLLow-level high-impedance-stateoutput leakage currentOE = VDD,VDD = MINVOL = 016AConditions marked MIN or MAX are as stated in recommended operating conditions.powerPARAMETERTEST CONDITIONSMINTYPMAXUNITIDDSupply currentf(CLK) = 20 MHz, National Television System Committee (NTSC)ramp wave input, reference resistor dissipation is separate1827mAIfReference voltage currentTLC5510Vref = REFT REFB = 2 V5.27.510.5mAIrefReference voltage currentTLC5510AVref = REFT REFB = 4 V10.41521mAConditions marked MIN or MAX are as stated in recommended operating conditions.static performancePARAMETERTEST CONDITIONSMINTYPMAXUNITSelf-bias (1), at REFBShort REFB to REFBSShort REFT to REFTS0.570.610.65Self-bias (2), REFT REFBShort REFB to REFBS,Short REFT to REFTS1.92.022.15VSelf-bias (3), at REFTShort REFB to AGND,Short REFT to REFTS2.182.292.4RrefReference voltage resistorBetween REFT and REFB190270350CiAnalog input capacitanceVI(ANLG) = 1.5 V + 0.07 Vrms16pFTLC5510f(CLK) = 20 MHz,TA = 25C0.40.75Integral nonlinearity (INL)TLC5510(CLK),VI = 0.5 V to 2.5 VTA = 20C to 75C1Integral nonlinearity (INL)TLC5510Af(CLK) = 20 MHz,TA = 25C0.40.75TLC5510A(CLK),VI = 0 to 4 VTA = 20C to 75C1LSBTLC5510f(CLK) = 20 MHz,TA = 25C0.30.5LSBDifferential nonlinearity (DNL)TLC5510(CLK),VI = 0.5 V to 2.5 VTA = 20C to 75C0.75Differential nonlinearity (DNL)TLC5510Af(CLK) = 20 MHz,TA = 25C0.30.5TLC5510A(CLK),VI = 0 to 4 VTA = 20C to 75C0.75EZSZero scale errorTLC5510Vref = REFT REFB = 2 V184368mVEZSZero-scale errorTLC5510AVref= REFT REFB = 4 V3686136mVEFSFull-scale errorTLC5510Vref = REFT REFB = 2 V20020mVEFSFull-scale errorTLC5510AVref = REFT REFB = 4 V40040mVConditions marked MIN or MAX are as stated in recommended operating conditions.TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20035POST OFFICE BOX 655303 DALLAS, TEXAS 75265operating characteristics at VDD = 5 V, VREFT = 2.5 V, VREFB = 0.5 V, f(CLK) = 20 MHz, TA = 25C (unlessotherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITfMaximum conversion rateTLC5510fI= 1 kHz rampVI(ANLG) = 0.5 V 2.5 V20MSPSfconvMaximum conversion rateTLC5510AfI = 1-kHz rampVI(ANLG) = 0 V 4 V20MSPSBWAnalog input bandwidthAt 1 dB14MHztd(D)Digital output delay timeCL 10 pF (see Note 1 and Figure 1)1830nsDifferential gainNTSC 40 Institute of Radio Engineers (IRE)1%Differential phaseg()modulation wave,fconv = 14.3 MSPS0.7degreestAJAperture jitter time30pstd(s)Sampling delay time4nstenEnable time, OE to valid dataCL = 10 pF5nstdisDisable time, OE to high impedanceCL = 10 pF7nsInput tone = 1 MHzTA = 25C45Input tone = 1 MHzFull range43Input tone = 3 MHzTA = 25C45Spurious free dynamic range (SFDR)Input tone = 3 MHzFull range46dBSpurious free dynamic range (SFDR)Input tone = 6 MHzTA = 25C43dBInput tone = 6 MHzFull range42Input tone = 10 MHzTA = 25C39Input tone = 10 MHzFull range39SNRSignal to noise ratioTA = 25C46dBSNRSignal-to-noise ratioFull range44dBNOTE 1:CL includes probe and jig capacitance.NN+1N+2N+3N+4N3N2N1NN+1td(D)CLK (clock)ANALOG IN(input signal)D1D8(output data)tw(H)tw(L)td(s)Figure 1. I/O Timing DiagramTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20036POST OFFICE BOX 655303 DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONfunctional descriptionThe TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each.As shown in Figure 2, input voltage VI(1) is sampled with the falling edge of CLK1 to the upper comparators blockand the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with therising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the risingedge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shownin Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.Input voltage VI(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, andLD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears withthe rising edge of CLK5.VI(1)VI(2)VI(3)VI(4)CLK1CLK2CLK3CLK4S(1)C(1)S(2)C(2)S(3)C(3)S(4)C(4)S(1)H(1)C(1)S(3)H(3)C(3)H(0)C(0)S(2)H(2)C(2)S(4)H(4)LD(2)OUT(2)OUT(1)OUT(0)OUT(1)ANALOG IN(sampling points)CLK (clock)Upper Comparators BlockUpper DataLower Reference VoltageLower Comparators Block (A)Lower Data (A)Lower Comparators Block (B)Lower Data (B) D1D8 (data output)UD(0)RV(0)UD(1)RV(1)UD(2)RV(2)UD(3)RV(3)LD(1)LD(0)LD(1)LD(2)CLK5Figure 2. Internal Functional Timing DiagramTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20037POST OFFICE BOX 655303 DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONinternal referencingTLC5510The three internal resistors shown with VDDA can generate a 2-V reference voltage. These resistors are broughtout on VDDA, REFTS, REFT, REFB, REFBS, and AGND.To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3.This connection provides the standard video 2-V reference for the nominal digital output.R1320 NOMRref270 NOMR280 NOMVDDA(analog supply)REFTSREFTREFBREFBSAGNDTLC5510161722212318Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor DividerTLC5510AFor an analog input span of 4 V, 4 V is supplied to REFT, and REFB is grounded and terminal connections shouldbe made as shown in Figure 4. This connection provides the 4-V reference for the nominal zero to full-scaledigital output with a 4 Vpp analog input at ANALOG IN.R1320 NOMRref270 NOMR280 NOMREFTSREFTREFBREFBSAGNDTLC5510A1617222123184 VVDDA(analog supply)Figure 4. External Connections for 4-V Analog Input SpanTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20038POST OFFICE BOX 655303 DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONfunctional operationThe output code change with input voltage is shown in Table 1.Table 1. Functional OperationINPUT SIGNALSTEPDIGITAL OUTPUT CODEINPUT SIGNALVOLTAGESTEPMSBLSBVref(B)255000000001280111111112710000000Vref(T)011111111APPLICATION INFORMATIONThe following notes are design recommendations that should be used with the device.?External analog and digital circuitry should be physically separated and shielded as much as possible toreduce system noise.?RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation andproduction process. Breadboards should be copper clad for bench evaluation.?Since AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible.A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog anddigital ground plane should be used on PCB layouts when additional logic devices are used. The AGNDand DGND terminals of the device should be tied to the analog ground plane.?VDDA to AGND and VDDD to DGND should be decoupled with 1-F and 0.01-F capacitors, respectively,and placed as close as possible to the affected device terminals. A ceramic-chip capacitor is recommendedfor the 0.01-F capacitor. Care should be exercised to ensure a solid noise-free ground connection for theanalog and digital ground terminals.?VDDA, AGND, and ANALOG IN should be shielded from the higher frequency terminals, CLK and D0D7.When possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB forshielding.?In testing or application of the device, the resistance of the driving source connected to the analog inputshould be 10 or less within the analog frequency range of interest.TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 20039POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONC1D1C3C4C5C6C2C11C9C7C8C10C12R5R4R2R1Q1D3D2TP3R3C11FB2FB3FB7FB1VREFADJTP1J1VDDDVDDAVDDAREFTSREFTVDDAANALOG INAGNDAGNDREFBSREFBDGND121110987654321131415161718192021222324CLKVDDDD8 (MSB)D7D6D5D4D3D2D1 (LSB)DGNDOETLC5510AVDD5 VClockOutputEnableDVDD5 VVideoInputJP2JP1JP4JP3 5 VNOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.LOCATIONDESCRIPTIONC1, C3C4, C6C120.1-F capacitorC210-pF capacitorC547-F capacitorFB1, FB2, FB3, FB7Ferrite beadQ12N3414 or equivalentR1, R375- resistorR2500- resistorR410-k resistor, clamp voltage adjustR5300- resistor, reference-voltage fine adjustFigure 5. TLC5510 Evaluation and Test SchematicTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 200310POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONC1D1C3C5C6C2C11C9C7C8C4R5R4R2R1Q1R3C11FB2FB3FB7FB1VREFADJTP1J1VDDDVDDAVDDAREFTSREFTVDDAANALOG INAGNDAGNDREFBSREFBDGND121110987654321131415161718192021222324CLKVDDDD8 (MSB)D7D6D5D4D3D2D1 (LSB)DGNDOETLC5510AAVDD5 VClockOutputEnableDVDD5 VVideoInput 5 VNOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired Q1 quiescent operating point.LOCATIONDESCRIPTIONC1, C3C4, C6C110.1-F capacitorC210-pF capacitorC547-F capacitorFB1, FB2, FB3, FB7Ferrite beadQ12N3414 or equivalentR1, R375- resistorR2500- resistorR410-k resistor, clamp voltage adjustR5300- resistor, reference-voltage fine adjustFigure 6. TLC5510A Evaluation and Test SchematicTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 200311POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONCLOCKCLOCKANALOG INOED1D2D3D4D5D6D7D8To Processor100 pF49.9 0.1 F4.7 F0.1 F+4.7 F+0.1 F4.7 F+FB1FB3_+0.1 F+4.7 FAVSS0.1 F4.7 F+1 kAVDD10 k POT1 k4.7 F49.9 VDDAVDDAVDDAREFTSREFT+4.7 F0.1 F4.7 F+REFBSREFB0.1 F4.7 F+AGNDAGND681 VDDDVDDDDGNDDGND0.1 F0.1 F4.7 FDVDDTLC5510THS3001681 5 V 5VFB Ferrite Bead5 VFigure 7. TLC5510 Application SchematicTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 200312POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATION50AVDD0.1F40249.9OPA69059698698+6.8F0.1F100pF4.7F0.1F4.7F0.1F4.7F0.1F0.1F4.7F4.7F4.7F0.1F4.7F0.1F+5VDVDD+5VTLC5510ACLOCKCLOCKANALOG INVDDAVDDAVDDAREFTSREFTREFBSREFBAGNDAGNDOED1D2D3D4To ProcessorD5D6D7D8VDDDVDDDDGNDDGNDFB1FB3VREF4V+ FB Ferrite Bead402Figure 8. TLC5510A Application SchematicTLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 200313POST OFFICE BOX 655303 DALLAS, TEXAS 75265MECHANICAL DATAPW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE14 PINS SHOWN0,65M0,100,100,250,500,750,15 NOMGage Plane289,809,60247,907,7020166,606,404040064/F 01/970,306,606,2080,194,304,5070,1514A11,20 MAX145,104,9083,102,90A MAXA MINDIMPINS *0,054,905,10Seating Plane08NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash or protrusion not to exceed 0,15.D.Falls within JEDEC MO-153TLC5510, TLC5510A8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERSSLAS095L SEPTEMBER 1994 REVISED JUNE 200314POST OFFICE BOX 655303 DALLAS, TEXAS 75265MECHANICAL DATANS (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE4040062/B 2/9514 PIN SHOWN2,00 MAXA0,05 MINSeating Plane1,050,55114PINS *5,605,0078,207,408A MINA MAXDIMGage Plane0,15 NOM0,259,909,9010,501410,501612,3014,7015,3012,9020240,101,27010M0,250,350,51NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash or protrusion, not to exceed 0,15.PACKAGING INFORMATIONOrderable DeviceStatus(1)PackageTypePackageDrawingPins PackageQtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)TLC5510AINSLEOBSOLETESONS24TBDCall TICall TITLC5510AINSRACTIVESONS242000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMTLC5510AINSRG4ACTIVESONS242000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMTLC5510INSLEOBSOLETESONS24TBDCall TICall TITLC5510INSRACTIVESONS242000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMTLC5510INSRG4ACTIVESONS242000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMTLC5510IPWACTIVETSSOPPW2460Green (RoHS &no Sb/Br)CU NIPDAULevel-2-260C-1 YEARTLC5510IPWG4ACTIVETSSOPPW2460Green (RoHS &no Sb/Br)CU NIPDAULevel-2-260C-1 YEARTLC5510IPWRACTIVETSSOPPW242000Green (RoHS &no Sb/Br)CU NIPDAULevel-2-260C-1 YEARTLC5510IPWRG4ACTIVETSSOPPW242000Green (RoHS &no Sb/Br)CU NIPDAULevel-2-260C-1 YEAR(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TIs terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.Important Information and Disclaimer:The information provided on this page represents TIs knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.In no event shall TIs liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.PACKAGE OPTION ADDENDUM18-Jul-2006AddendumTAPE AND REEL INFORMATION*All dimensions are nominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1 (mm)A0 (mm)B0 (mm)K0 (mm)P1(mm)W(mm)Pin1QuadrantTLC5510IPWRTSSOPPW242000330.016.46.916.0Q1PACKAGE MATERIALS INFORMATION11-Mar-2008Pack Materials*All dimensions are nominalDevicePackage TypePackage DrawingPinsSPQLength (mm)Width (mm)Height (mm)TLC5510IPWRTSSOPPW242000346.0346.033.0PACKAGE MATERIALS INFORMATION11-Mar-2008Pack Materials MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999POST OFFICE BOX 655303 DALLAS, TEXAS 75265PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE14 PINS SHOWN0,65M0,100,100,250,500,750,15 NOMGage Plane289,809,60247,907,7020166,606,404040064/F 01/970,306,606,2080,194,304,5070,1514A11,20 MAX145,104,9083,102,90A MAXA MINDIMPINS *0,054,905,10Seating Plane08NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash or protrusion not to exceed 0,15.D.Falls within JEDEC MO-153IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
- 温馨提示:
1: 本站所有资源如无特殊说明，都需要本地电脑安装OFFICE2007和PDF阅读器。图纸软件为CAD,CAXA,PROE,UG,SolidWorks等.压缩文件请下载最新的WinRAR软件解压。
2: 本站的文档不包含任何第三方提供的附件图纸等，如果需要附件，请联系上传者。文件的所有权益归上传用户所有。
3.本站RAR压缩包中若带图纸，网页内容里面会有图纸预览，若没有图纸预览就没有图纸。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 人人文库网仅提供信息存储空间，仅对用户上传内容的表现方式做保护处理，对用户上传分享的文档内容本身不做任何修改或编辑，并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容，请与我们联系，我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
人人文库网所有资源均是用户自行上传分享，仅供网友学习交流，未经上传用户书面授权，请勿作他用。
川公网安备: 51019002004831号