数字逻辑电路课程设计-4bit模9加法器-VHDL实现含完整

电子科技大学

UNIVERSITYOFELECTRONICSCIENCEANDTECHNOLOGYOFCHINA

数字逻辑设计

实验报告

实验题目：dbit模9加法器

学生姓名：

指导老师：

一、实验内容

设计一个4bit模9加法器。输入为两个4bit的二进制数，输出为两数相加后模9的结果。其

数学表达式为：y-(xl+x2)mod9。

二、实验要求

1、功能性要求：

能够实现4bit无符号数的旗9加法运算，即输入两个4比特数据时能够正确输出其相加并模

9运算结果。

2、算法要求：

模加法器有多种算法，可采用任意算法进行设计。

3、设计性要求：

采用全加器、半加器和根本门结构化描述。能够编写TestBench文件，并利用Modclsim进行

仿真。在Modelsim仿真正确的基础上，能够生成bit文件并上板验证其正确性。

4、根本上板要求：

在上板实验时，输入的两个4bit数采用拨码开关输入，输出采用LED灯进行显示。

三、设计思路

1、整体思路：

为了实现4bit无符号数的模9加法运算，可以先将两个4bit的加数a和b先分别模9,相加

之后再模9得到最终结果。

2、模9器：

先找出读入的5bit数与模9后的4bit数之间的关系，画出卡诺图，再根据卡诺图得出其相应

的逻辑表达式即可。设读入的5bit数为ca门/、a、b、c、d,模9后得到的4bit数为队x、y、z。

则化简后得到的逻辑表达式分别为：

w=carryrab'c'd',

x=carryrbe+carryJa'b+carry'bd+carrya'b'c'd',

y=carry"a'c+carryycd+carry,abc'd'+carrya,b'c'd',

z=carry*a'd+carry'acd,+carry'abd'+carrya'b'c'd'0

3、全加器：

全加器可以实现两个Ibit数a、b和进位输入cin的相加，其真值表如下所示：

ABCmSUM(S)Cout

00000

00110

01010

01101

10010

10101

11001

11111

这里全加器由半加器和或门构成，其原理图如下:

A

Cout

B

4、半加器：

半加器是全加器的根本组成单元，可以实现两个Ibit数a和b的相加，并将进位输出，其真

值表如下：

ABSC

000C

011C

1010

1101

半加器由一个异或门和一个与门构成，其原理图如下所示:

A

S=A.B+A.B

B

C=A.B

5、数码管显示：

单个数码管一共有7个端(不含小数点)，用来表示组成一个数字的7个局部，故只要找到这

7个段和模9后的4bit数间的对应关系，将其画出卡诺图并化简成逻辑表达式即可。设得到的4bit

数为a、b、c、d,则得到的7段disa'disg的表达式为：

disa=b+d+c'a'+ac;

disb=c,+d+b'a'+ab;

disc=a+b'+c+d;

disd=ba'+c'a'+c'b+cb'a;

dise=d+ba'+c'a';

disf=d+b'a'+ca'+cb':

disg=d+ba'+c'b+ca'+cb';

四、程序设计

1、顶层：

entitymainis

Port(al:inSTD_L0GIC;

a2:inSTI)_L0GIC;

a3:inSTD_LOGIC;

«4:inSTDJOGTC：

bl:inSTD_L0GIC;

b2:inSTD_LOGIC;

b3:inSTD_L0GIC;

b4:inSTD_L0GIC;

ansi:outSTI)_LOGIC;

ans2:outSTD_LOGIC;

ans3:outSTI)_LOGIC;

ans4:outSTDLOGIC;

disA:outSTDJOGIC;

disB:outSTDLOGIC;

disC:outSTD_L0GIC;

disD:outSTD_LOG1C;

disE:outSTD_L0GIC;

disF:outSTDJOGIC;

disG:outSTDLOGIC

)；

endmain;

architectureBehavioralofmainis

COMPONENTfulladder

PORT(

a:INstdlogic;

b:INstdlogic;

ci:INstd_logic;

s:OUTstdlogic;

co:OUTstd_logic

)；

ENDCOMPONENT;

COMPONENTmod9

PORK

carry:INstdlogic;

a:INstd_logic;

b:INstdlogic;

c:INstd_logic;

d:INstdlogic;

w:OUTstd_logic;

x:OUTstd_logic;

y:OUTstdlogic;

z:OUTstd_logic

)；

ENDCOMPONENT;

COMPONENTdis

PORT（

a:TNstd_logic

b:INstd」ogic

c:INstdlogic

d:INstd_logic

disa:OUTstdlogic;

disb:OUTstd_logic;

disc:OUTstdlogic;

disd:OUTstd_logic;

dise:OUTstdlogic;

disf:OUTstdlogic;

disg:OUTstd_logic

）；

ENDCOMPONENT;

signal

cl,c2,c3,c4,si,s2,s3,s4,ansi1,ans22,ans33,ans44,all,a22,a33,a44,bll,b22,b33,b44,temp:stdlogic;

begin

一mod9_a—

temp<=，0，;

Inst_mod9_a:mod9PORTMAP（

carry=>temp,—carry是最高位

a=>a4,

b=>a3,

c=>a2,

d=>al,-d是最低位

w=>a44,-w是最高位

x=>a33,

y=>a22,

z=>all-z是最低位

）；

-mod9_b—

Inst_mod9_b:mod9PORTMAP（

carry=>temp,--carry是最高位

a=>b4,

b=>b3,

c=>b2,

d=>bl,—d是最低位

w=>b44,—w是最高位

x=>b33,

y=>b22,

z=>bll—z是最低位

）；

——add——

Inst_fulladder_addl:fulladderPORTMAP(

a=>al1,

b=>bll,

ci=>temp,

s=>si,

co=>cl

)；

Tnst_ful1adder_add2:fulladderPORTMAP(

a=>a22,

b->b22,

ci=>cl,

s=>s2,

co=>c2

)；

Inst_fulladder_add3:fulladderPORTMAP(

a=>a33,

b=>b33,

ci=>c2,

s=>s3,

co=>c3

)；

Inst_fulladder_add4:fulladderPORTMAP(

a=>a44,

b=>b44,

ci=>c3,

s=>s4,

co=>c4

)；

-mod9_ans-

Inst_mod9_ans:mod9PORTMAP(

carry=>c4,一carry是最高位，对应最后一个进位c4

a=>s4,

b=>s3,

c=>s2,

d=>si,-d是最低位，对应si

w=>ans44,一w是最高位，对应ans4

x=>ans33,

y=>ans22,

z=>ansi1-z是最低位，对应ansi

）；

cinsl<=notansll;

ans2<=notans22;

ans3<=notans33;

ans4<=notans44;

Inst_dis:disPORTMAP(

a=>ansll,一最低位(读入取反之前的ans)

b->ans22,

c=>ans33,

d=>ans44,一最高位

disa=>disA,

disb=>disB,

disc=>disC,

disd=>disD,

disc=>disE,

disf=>disF,

disg=>disG

)；

endBehavioral;

2、模9器：

entitymod9is

Port(carry:inSTD_LOGIC;

a:inSTD_LOGIC;

b:inSTD_LOGIC;

c:inSTD_LOGIC;

d:inSTD_LOG1C;

w:outSTDLOGIC;

x:outSTDJ.OGIC;

y:outSTDLOGIC;

z:outSTDLOGIC);

endmod9;

architectureBehavioralofmod9is

signalnota,noth,note,notd,notcarry:std_logic;

Begin

——not一

nota<=inota

notb<=inotb

notc<=niotc

notd<=1notd

notcai'ry<=notcarry;

一mod9一

w<=aandnnthandnnteandnntdandnotcarry;

x<=(bandc)or(bandnota)or(bandd);

y<=(notaandc)or(candd)or(aandbandnoteandnotd);

z<=(notaandd)or(aandcandnotd)or(aandbandnotd);

endBehavioral;

3、全加器：

entityfulladderis

Port(a:inSTD_LOGIC;

b:inSTD_LOGIC;

ci:inSTDLOGIC;

s:outSTDLOGIC;

co:outSTD_LOGIC);

endfulladder;

architectureBehavioraloffulladderis

COMPONENThalfadder

PORK

a:INstdlogic;

b:INstd_logic;

s:OUTstdlogic;

c:OUTstd_logic

);

ENDCOMPONENT;

COMPONENTor2i

PORK

i1:INstdlogic;

i2:INstd_logic;

o:OUTstdlogic

)；

ENDCOMPONENT;

signalsi,cl,c2:std_logic;

begin

Inst_halfadder_suml:halfadderPORTMAP(

a=>a,

b=>b,

s=>si,

c=>cl

);

Insthalfaddersum2:halfadderPORTMAP(

b=>si,

s=>s,

c=>c2

)；

Inst_or2i_co:or2iPORTMAP(

il=>cl,

i2=>c2,

o=>co

);

endBehavioral;

4、半加器：

entityhalfadderis

Port(a:inSTD_LOGIC;

b:inSTD_L(X；1C;

s:outSTDLOGIC;

c:outSTD_LOGIC);

endhalfadder;

architectureBehavioralofhalfadderis

COMPONENTnoli

PORT(

i:INstd_logic;

o:OUTstd_logic

)；

ENDCOMPONENT;

COMPONENTand2i

PORT(

i1:INstd_logic;

i2:INstd_logic;

o:OUTstdlogic

)；

ENDCOMPONENT;

COMPONENTor2i

PORK

i1:INstdlogic;

i2:INstd_logic;

o:OUTstd_logic

)；

ENDCOMPONENT;

signalnota,noth,s1,s2:s1.d_logic:

begin

—not—

Inst_noti_nota:notiPORTMAP(

i=>a,

o=>nota

Inst_noti_notb:notiPORTMAP(

i=>b,

o=>noth

Inst_and2i_sl:and2iPORTMAP(

il=>nota,

i2=>b,

o=>si

Inst_and2i_s2:and2iPORTMAP(

il=>a,

i2=>noth,

o=>s2

Instor2is:or2iPORTMAP(

i1=>si,

i2=>s2,

o=>s

Inst_and2i_c:and2iPORTMAP(

il=>a,

i2=>b,

o=>c

)；

endBehavioral;

5、数码管显示：

entitydisis

Port(a:inSTD_LOGIC;

b:inSTDJ.OGIC;

c:inSTDLOGIC;

d:inSTD_LOGIC;

disa:outSTD_LOGIC;

disboutSTDLOGIC;

diACoutSTDJOGIC：

disdoutSTD一LOGIC;

diseoutSTDLOGIC;

disfoutSTD_LOGIC;

disgoutSTD_LOGIC)

enddis;

architectureBehavioralofdisis

signalnota,noth,note,notd,disaa,disbb,discc,disdd,disee,disff,disgg:stdlogic;

begin

nota<=nota;

notb<=notb;

notc<=notc;

notd<=notd;

disaa<=bordor(noteandnota)or(canda);

disbb<=notcordor(notbandnota)or(banda);

discc<=aornotborcord;

disdd<=(bandnota)or(noteandnota)or(noteandb)or(candnotbanda);

disee<=dor(bandnota)or(noteandnota);

disff<=dor(notbandnota)or(candnota)or(candnotb);

disgg<=dor(bandnota)or(noteandb)or(candnota)or(candnotb);

disa<=notdisaa;

disb<=notdisbb;

disc<=notdiscc;

disd<=notdisdd;

dise<=notdisee;

disf<=notdisff;

disg<=notdisgg;

endBehavioral;

五、仿真与硬件调试

1、仿真：

（1）顶层仿真

1.仿真文件：

LIBRARYieee;

USEieee.stdlogic1164.ALL;

ENTITYtest2IS

FNDtps?t2;

ARCHITECTUREbehaviorOFtest2IS

—ComponentDeclarationfortheUnitUnderTest(UUT)

COMPONENTmain

PORT(

al:INstc_logic;

a2:INstd_logic;

a3:INstdlogic;

a4:[Nstdlogic;

bl:INstd_logic;

b2:INstdlogic;

b3:INstd_logic;

b4:INstd_logic;

ansiOUTstd_logic;

ans2OUTstdlogic;

ans3OUTstdlogic;

ans4OUTstdlogic;

disAOUTstdlogic;

disBOUTstd」ogic;

disCOUTstdlogic;

disi)OUTstd_logic;

disEOUTstdlogic;

disFOUTstdlogic;

disGOUTstdlogic

)；

ENDCOMPONENT;

-Inputs

signalal:std_logic:='O'

signala2:std_logic:='()'

signala3:std_logic:='O'

signala4:stdlogic:='O'

signalbl:std_logic:='O'

signalb2:stdlogic:='O'

signalb3:std_logic:='O'

signalb4:stdlogic:='O'

-Outputs

signalansistd_logic;

signcilans2std一logic;

signalans3stdlogic;

signalans4std_logic;

signaldisAstdlogic;

signaldisBstd_logic;

signaldisCstdlogic;

signaldi<?td_lngic：

signaldisEstd一logic;

signaldisFstdlogic;

signcildisGstd_logic;

-Noclocksdetectedinportlist.Replace<clock>belowwith

一一appropriateportname

BEGIN

InstantiatetheUnitUnderTest(UUT)

uut:mainPORTMAP(

al=>al,

a2=>a2,

a3=>a3,

a4=>a4,

bl=>bl,

b2=>b2,

b3=>b3,

b4=>b4,

ansi=>cinsl,

ans2=>ans2,

ans3=>ans3,

ans4=>ans4,

disA=>disA,

disB=>disB,

disC=>disC,

disD=>disD,

disE=>disE,

disF=>disF,

disG=>disG

)；

Stimulusprocess

stim_proc:process

begin

a4<='O';a3<='O'a2<=，0，;al<='O';

b4<='O';b3<='()'h2<='()';bl<='O';

waitfor100ns;

a4<='O';a3<='O'a2<=50*;al<='O';

b4<='O';b3<='O'b2<='O';bl<='T;

waitfor100ns;

a4<='O';a3<='O';a2<='()';al〈二'O';

b4<='O';b3<='O';b2"'1';bl<='O';

waitfor100ns;

a4<='O';a3<=O';a2<='O';al<='O';

b4<='O';b3<=O';b2<=*T;bl<二'「；

waitfor100ns;

a4<='O';a3<=O';a2号'O';al<='O';

b4<='O';b3<=1';b2<='()';bl<='O';

waitfor100ns;

a4<='O'a3<='O';a2<='O'al<='O';

b4<='O';b3<='1';b2<='O'bl<='1';

waitfor100ns;

a4<='()';a3<='O';a2<='()'al<='O';

b4<='O'b3<='T;b2<=*T;bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='O';al<='O';

b4<='O';b3<='1';b2<=JT;bl<=1r；

waitfor100ns;

a4<='O';a3<='O'a2<='O';al<='O';

b4<='1';b3<='O'b2<='O';bl<='O';

waitfor100ns;

a4<='O';a3<='O'ci2<='O';al<='O';

b4<=T';b3<='O';b2<='O';bl<='1';

waitfor100ns;

a4<='O';a3<=O';a2<='O';al<='O';

b4<='1';b3<=O';b2<='1';bl<='O';

waitfor100ns;

a4<='O';a3<=O';a2<='O';al<='O';

b4<='T;b3<=O';b2<=*T;bl<二'1'；

waitfor100ns;

a4<='O'a3<='O';a2<='O'al<='O';

b4<='1'b3<='1';b2<='O'bl<='O';

waitfor100ns;

a4<='O';a37'O';a2<=，0’;al<='O';

b4<='1';b3<='1';b2<=，0，;bl<='1';

waitfor100ns;

a4<='O'a3<='O'：a2<='O'al<='O'；

b4<='1'b3<=f;b2<='1';bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='O';al<='O';

b4<='1';b3<='1';b2<='1';bl<=*r；

waitfor100ns;

a4<='O'a3<='O';a2<='O';al<=*r;

b4<-'O'；b3<-O';b2<-'O'；bl<一'O'；

waitfor100ns;

a4〈二'O';a3〈二'O';a2<=，0，;al<=1'；

b4<='O';b3<='O'b2<='O';bl<='1';

waitfor100ns;

a4<='O';a3<=O';a2<='O';al<=*r；

b4烂'O';b3<=O';b2<='1';bl<='o'；

waitfor100ns;

a4<='O';a3<=0*;a2<='O';al<=,r；

b4<='O';b3<=()';b2<='1';bl<='i'；

waitfor100ns;

a4<='O';a3<='O';a2<='O'al<=*1*;

b4<='O';b3<='1';b2<='O'bl<='O';

waitfor100ns;

a4<='O'a3<='O';a2<='O'al<=*r;

b4<='O'b3<='1';b2<='O'bl<='1';

waitfor100ns;

a4<='O';a3<='O';a2<='O';al<='1';

b4<='O';b3<=T;b2<=11*;bl<=，0，;

waitfor100ns;

a4<='O'a3<='O';a2<='O';al<='1'；

b4<='O';b3<='1';b2<=1';bl<=1r；

waitfor100ns;

a4<='O';a3<='O';a2<=，0，;al<=*r;

b4<='1';b3<='O';b2<=，0，;bl<='O';

Wciitfor100ns;

a4〈二'O';a3〈二'O';a2<='O';al<=*1*;

b4<=*r;b3<='O';b2<='O';bl<=1r;

w«itfor100ns;

a4<='O';a3<='O';a2<='O';al<='1';

b4<=，］，;b3<=，0，;b2"，］，;bl<=，0，;

waitfor100ns;

a4<='O';a3<='O';a2<='O';al<='1';

b4<='1';b3<='()';b2<=1';bl<=,r;

waitfor100ns;

a4<='O'a37'O';a2<='O'al<=，］，;

b4<=T'b3<=1T;b2<='O'bl<='O';

waitfor100ns;

a4<='O';a3<='()';a2<='()';al<:'1';

b4<='1';b3<=V;b2<='O';bl<='1';

waitfor100ns;

a4<='O'a3<='O';a2<='O'al<=

b4<='Tb3<=1*；b2<='1';bl<='O';

waitfor100ns;

a4<='O'a3<='O';a2<='O';al＜二'1'；

b4<=T'b3<=1';b2<='1';bl<='1';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='O';b3<='O';b2<='O';bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='O';b3<='O';b2<=*0*;bl<=，］，;

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='O';b3<='O';b2<='I';bl<='O';

waitfor100ns;

a4<='O';a3<=#0*;a2<='V;al<='O';

b4<='O';b3<='()';b2<='1';bl<='1';

waitfor100ns;

a4<='O';a3<='O';a2〈='I';al<='O';

b4<='O';b3<='1';b2<='O';bl<='O';

waitfor100ns;

M<='0-='O'：狗2<='1';al<=,0,；

b4<='O';b3<=*f;b2<='O';bl<=，］，;

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='O';b3<='1';b2<=*T;bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<=，］，;al<='O';

b4<->0*;b3<-T';b2<-*f；bl<-*r；

waitfor100ns;

a4<='O';a3<='O';a2<='1';al烂'O';

b4<='1';b3<='O';b2<='O';bl<='O';

waitfor10()ns;

a4<='O';a3<='O';a2<=，］，;al<=，0，;

b4<='1';b3<='O';b2<='O';bl<:'1';

wailfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='1';b3<='()';b2<='1';bl<='0,；

waitfor100ns;

a4<='O';a3<='O';a2<='1';al仁’O';

b4<=T';b3<="；b2<='1';bl<='1';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<=*T;b3<=*I*;b2<='O';bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='O';

b4<='1';b3<='1';b2<='O';bl<二'1'；

waitfor100ns;

a4<='O';a3<='O';a2<=I*;al<='O';

b4<='1';b3<='1';b2<=V;bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<=*T;al<二，0，；

b4<=T';b3<='1';b2<='1';bl<='T;

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='1';

b4<='O';b3<='O';b2<='O';bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='1'；

b4〈二'O';b3<='O'b2<='O';bl<=*1*;

waitfor100ns;

a4<='O';a3<='O';a2<=I*;al<='1';

b4<='O'b3<='O'b2<='1';bl<='O';

waitfor100ns;

a4<='O'a3烂'O';a2〈二'1';al<=*r；

b4<='O';b3<='O';b2<=，］，；bl<=Jr；

waitfor100ns;

1

a4<='O';a3<='O';a2<=C;al<二'1'；

b4号'O';b3<='1'b2<='O';bl<=10*;

waitfor100ns;

a4<='O'a3<='O';a2<=T';al<='1';

b4<='O'b3<='1';b2<='O';bl<=*1*;

waitfor100ns;

a4妇'O';a3<='O';a2<='T;al<二'1'；

b4<='O'b3<='1';b2<='1';bl<='O';

waitfor100ns;

a4<='O'a3<='O';a2<='1';al<二'「；

b4<='O'b3<=T';b2<='1';bl<='1'；

waitfor100ns;

a4<='O';a3<=';a2<='1';al<:'1'；

b4<二'1';b3<='O';b2<=*0*;bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<=

b4<='1b3<='O'b2〈二'O';bl<=r；

waitfor100ns;

a4<='O';a3<='O'a2<=*T;al<='1';

b4<='1';b3<='O'b2<='1';bl<='O';

waitfor100ns;

a4<='O';a3<='O'a2<=*T;al<=，］，;

b4<=*1*;b3<='O'b2<='1';bl<='1';

waitfor100ns;

a4<='O'：a3<='O'：<=V;al<=*r：

b4<='1';b3<=1T;b2<=O';bl<='O';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<='1';

b4<='1';b3<='1';b2<='O';bl<='1';

waitfor100ns;

a4<='O';a3<='O';a2<='1';al<=*1*;

b4<-'1';b3<-'1';b2<-'1';bl<-'O'；

waitfor100ns;

a4〈二'O';a3<='O';a2<='1';al<=1'；

b4<='1';b3<=*T;b2<='1';bl<=1'；

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<='O';b3<='O'b2<='O';bl<=，0，;

waitfor100ns;

a4<='O';a3<='1';a2<='O'al<='O';

b4<='O';b3<='()';b2<='()'bl<='1';

waitfor100ns;

a4<='O'a3<=*I*;a2<='O'al<='O';

b4<='O';b3<='O'b2<=，］，;bl<='O';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<='O';b3<='O';b2<='1';bl'1'；

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<='O';b3<='1';b2<二'O';bl<=*0*;

waitfor100ns;

a4〈='O';a3<='1';a2<=*0*al<='O';

b4<='()';b3<='1';b2<='()'bl<=,r;

waitfor100ns;

a4<='O';a3<=1';a2<='O'al<='O';

b4<='O';b3<='1';b2<=，］，；bl<='O';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<='O';b3<='1';b2<='1';bl<='1';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='0,；

b4<='1';b3<='O';b2〈='O';bl<=*0*;

waitfor100ns;

a4<='O'a3<=，］，;a2<=，0，;al<='O';

b4<='1';b3<='()';b2<='()'bl<='1';

waitfor100ns;

a4<='O'a37’1';a2<=*0*;al<='O';

b4<=T'b3<='O';b2<='1';bl<='O';

waitfor100ns;

a4<='O';a3<=r;a2<='()';al<='O';

b4<='1';b3<=O';b2<=*f;bl<=1r；

waitfor100ns;

a4<='O';a3<=1';a2<='O'al<='O';

b4<=，］，;b3<=I*;b2<='O'bl<='O';

waitfor100ns;

a4<='O'a3<=*I*;a2<=O';al<='O';

b4<=T'b3<='1';b2<=O';bl<='1';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<=T';b3<=T';b2<='1';bl<='O';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='O';

b4<=>r；b3<='i'；b2<=jr；bi<=,r；

waitfor100ns;

a4<='O';a3<=T';a2<='O';al<='1';

b4<='O';b37'O';b2<='O';bl<='O';

waitfor100ns;

a4<=，0，;a3<=，T;a2<='O'al<=*r;

b4<='O'b3<='()'b2<='O';bl<='1';

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<='1';

b4<='O';b3<='O';b2<='1';bl<='O';

waitfor100ns;

a4<='O'：<=>r：a?'O';AlV：

b4<='O';b3<='O';b2,r；bir；

waitfor100ns;

a4<='O';a3<=*T;a2'O'；al'1'；

b4<='O';b3Hb2'O'；bl'O'；

waitfor100ns;

a4<='O';a3<=*T;a2'O'；al*r；

b4<一'O'；b3<一'1';b2'O'；bl'i'；

waitfor100ns;

a4<='O';a3<=JT;a2'O'；al」’；

b4<='O';b3<='1'；b2r；bi'O'；

waitfor10()ns;

a4<='O';a3<='1';a2'O';al」’；

b4<='O';b3<=1；b2'1';bl」'；

waitfor100ns;

a4<='O';a3<='1';a2'O';al」’；

b4<='；b3<='()';b2bl'O'；

waitfor100ns;

a4<='0>;a3<='1';a2<='O'；al*r；

b4<=T';b3<='O';b2<='O'；bl」'；

waitfor100ns;

a4<='O';a3<=1';a2'O'；al

b4<=*r;b3<='O';b2<='1';bl'O'；

waitfor100ns;

a4<='O';a3<='1';a2<='O';al<=1'；

b4<='1';b3<:'O';b2<='1';bl<=r；

waitfor100ns;

a4<='O'a3<=*I*;a2<=*0*;al＜二'1'；

b4<='1';b3<='1b2<='O';bl<='O';

waitfor100ns;

a4<='O'a3<=，］，;a2<='O';al<=*r;

b4<='1'b3<='1';b2<='O