教程讲稿ni培训lesson fpga programming techniques

1、Lesson 3FPGA Programming BasicsIntroductionDefining FPGA Logic with LabVIEWFPGA VI Development Process Developing the FPGA VIFront Panel CommunicationTesting with the EmulatorCompiling the FPGA VIA. IntroductionFPGA Layout and ComponentsHow FPGA WorksProgrammable interconnect switches and wires rout

2、e signals in an FPGA.Switches are known as Register Flip-Flops.Flip-Flops pass data on a rising edge of the clock.Compiled LabVIEW code produces a Look-up Table (LUT).LUT defines the interconnections between configurable logic blocks (CLBs).How FPGA Works (continued)Implements a VI that calculates a

3、 value for F from inputs A, B, C, and D where F = CD(A + B)Hardware ComparisonsMost important specification is number of logic slicesSlices help to represent the amount of logic that can implemented on a single FPGAWays to conserve FPGA space are covered in more detail in Lesson 8: FPGA Optimization

4、FPGA Family SpecificationsComponent Type1M Gate FPGA(PCI-7831R)3M Gate FPGA(PCI-7833R)Equivalent number of logic cells11,52032,256Number of logic slices 5,12014,336Available embedded RAM (bytes)81,920196,608B. Defining FPGA Logic with LabVIEWFPGA ModuleDo not have to learn VHDLTrue parallel executio

5、nDeterministicCompiling LabVIEW VIs to FPGA HardwareConvert the FPGA VI into executable codeFPGA Module compiles VIGraphical code translated to VHDL Xilinx ISE compiler creates circuit from VHDLCompiler optimizes the implementationA bitstream file resultsBitstream loads at run timeBitstream reloads

6、at power-upOn-board flash memoryController over PCI BusBenefits of FPGA Logic in LabVIEWFPGA provides:TimingTriggeringProcessingCustom I/OEach fixed I/O uses a portion of the FPGA logicThe PCI interface also uses a portion of the FPGA logicC. FPGA VI Development ProcessKeep in mindNo operating syste

7、m on the FPGADownload and run one top-level VI at a time FPGA can run independently of the hostFPGA can store dataEditing a VI in the FPGA Target activates the FPGA paletteInteger math and fixed-point mathD. Developing the FPGA VIFPGA is fast and reliableFPGA has limited space FPGART and/or PCTime c

8、ritical controlExtensive analysisAcquisitionFile I/OTiming in the FPGA User interfaceIn-line processingSupervisory controlTriggeringAdd a VI Under the FPGA TargetDemonstrationCreate an FPGA VI and explore the Functions palette supported under FPGA.E. Front Panel CommunicationFPGA Front PanelUse simp

9、le controls and indicatorsUse controls and indicators only when the value will be needed on the hostUse temporary controls and indicators for debuggingInteractive Front Panel CommunicationInteractive Front Panel Communication (continued)FPGA has no user interfaceMust communicate data from FPGA to ho

10、st PCRequires no additional programmingFront panel displays on host PCBlock diagram executes on FPGA as compiledCommunication layer shares all control and indicator valuesCannot use debugging tools when running FPGA VITest with Emulator first, or add indicators as probesF. Testing with the EmulatorC

11、ompilingfew minutes to several hoursVerify logic before compilingLabVIEW bit-accurate emulation modeExecutes logic on the Windows PCTraditional debugging tools are availableTwo kinds of emulationRandom data for inputsTarget hardware for I/OUsing the EmulatorRight-click the FPGA Target in the Project

12、 Explorer window and select Properties.Select General.Select an Emulator option.Click OK.Run the VI.*Set the Emulator to Off after testExercise 3-1: Creating a LabVIEW FPGA VICreate a VI that adds two numbers and runs a benchmark in parallel that determines how fast code is running.Run the VI in emu

13、lation mode and use debugging tools.G. Compiling the FPGA VIClick RunConverts graphical code to VHDLGenerates intermediate filesCompiling VI for FPGA Dialog Box Disconnect Disconnects from the Compile Server so that you can continue working in LabVIEWFollow instructions in the dialog box to reconnec

14、tLabVIEW FPGA Compile Server Dialog BoxToolsFPGA ModuleStart Local Compile Server to view previous compile reportsClick Compile ListSuccessful Compile ReportExercise 3-2: Compile a LabVIEW FPGA VICompile the application created in Exercise 3-1.SummaryQuiz1.The FPGA VI runs in an operating system on the FPGA processor.a.Trueb.False2.You must know VHDL programming to reconfigure the FPGA.a.Trueb.FalseSummaryQuiz3.The FPGA can achieve t