基于单片机外文翻译中英文翻译外文文献翻译

1、英文原文Description The at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory PEROM and 128 bytes RAM. The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry stan

2、dard MCS-51. instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Features: . Compatible with MCS-51. Prod

3、ucts . 4K Bytes of In-System Reprogrammable Flash Memory . Endurance: 1,000 Write/Erase Cycles . Fully Static Operation: 0 Hz to 24 MHz . Three-Level Program Memory Lock . 128 x 8-Bit Internal RAM . 32 Programmable I/O Lines . Two 16-Bit Timer/Counters . Six Interrupt Sources . Programmable Serial C

4、hannel. Low Power Idle and Power Down ModesThe at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In additio

5、n, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM c

6、ontents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description: VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins,

7、 the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code

8、bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pul

9、lups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current IIL because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with inter

10、nal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current IIL because of the internal pullups. Port

11、 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses MOVX DPTR. In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses MO

12、VX RI, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source

13、 four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current IIL because of the pullups. Port 3 also serves the functions of various special features of the

14、 at89s52 as listed below: Port pin alternate functions Port 3 also P3.0 rxd serial input port P3.1 txd serial output port receives some P3.2 int0 external interrupt0 control signals for P3.3 int1 external interrupt1 Flash programming P3.4 t0 timer0 external input and verification. P3.5 t1 timer1 ext

15、ernal input RST P3.6 WR external data memory write Reset input. A P3.7 strobe high on this pin for rd external data memory read strobe two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during acce

16、sses to external memory. This pin is also the program pulse input PROG during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each a

17、ccess to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in exte

18、rnal execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the at89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP E

19、xternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal progr

20、am executions. This pin also receives the 12-volt programming enable voltageVPP during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Osc

21、illator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2

22、 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications

23、must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any ena

24、bled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal

25、 RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Status of Exter

26、nal Pins During Idle and Power Down Modesmode Program memory ALE psen PortPortPortPortidle internal 1 1 0 1 2 3 data data data Data Idle External 1 float Data data Data 1 Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down Mode In the power down mode t

27、he oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not

28、 change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed U or can be pr

29、ogrammed P to obtain the additional features listed in the table below: Lock Bit Protection Modes When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that val

30、ue until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash ：The at89s52 is normally shipped with the on-chip Flash memory array in the erased state that is, cont

31、ents = FFH and ready to be programmed. The programming interface accepts either a high-voltage 12-volt or a low-voltage VCC program enable signal.The low voltage programming mode provides a convenient way to program the at89s52 inside the users system, while the high-voltage programming mode is comp

32、atible with conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Vpp=12v Vpp=5v Top-side at89s52 at89s52 mark xxx

33、x xxxx-5 signature yyww yyww 030H=1EH 030H=1EH 031H=51H 031H=51H 032H=FFH 032H=05H The at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using

34、the Chip Erase Mode. Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps. 1. Input the desired memory location on the address

35、lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typi

36、cally takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte

37、 written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can als

38、o be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back

39、via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase : The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the prope

40、r combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “ 1” s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes : The signature bytes are read by the same procedure as a normal verif

41、ication of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. 030H = 1EH indicates manufactured by Atmel 031H = 51H indicates 89C51 032H = FFH indicates 12V programming 032H = 05H indicates 5V programming Programming Interface

42、 Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. 中文翻译 描述at89s52 是美国 ATMEL公司生产的低电压,高性能CMOS8位单片机,片内含4Kb

43、ytes 的快速可擦写的只读程序储备器（PEROM）和 128 bytes 的随机存取数据储备器（ RAM）,器件采纳 ATMEL公司的高密度、非易失性储备技术生产,兼容 标准 MCS-51产品指令系统, 片内置通用 8 位中心处理器 （CPU）和 flish 储备单 元,功能强大 at89s52 单片机可为您供应很多高性价比的应用场合,可敏捷应用于各种掌握领域；主要性能参数：与 MCS-51产品指令系统完全兼容 4K字节可重复写 flash 闪速储备器 1000 次擦写周期 全静态操作： 0HZ24MHZ 三级加密程序储备器128*8 字节内部 RAM 32 个可编程 I/O 口 2 个 1

44、6 位定时计数器 6 个中断源 可编程串行 UART通道低功耗闲暇和掉电模式功能特性概述AT89S52供应以下标准功能： 4K 字节 flish 32 个 I/O 口线,两个 16 位定时计数器,一个 工串行通信口,片内振荡器准时钟电路；同时,闪速储备器,128 字节内部 RAM,5 向量两级中断结构,一个全双 at89s52 可降至 0HZ的静态规律操作,并支持两种软件可选的节电工作模式；闲暇方式停止 CPU的工作, 但答应RAM,定时计数器,串行通信口及中断系统连续工作；掉电方式储存 RAM中的内容,但振荡器停止工作并禁止其它全部部件工作直到下一个硬件复位；方框图引脚功能说明Vcc：电源电

45、压GND：地P0口：P0口是一组 8 位漏极开路型双向I/O 口,也即地址 / 数据总线复位口；作为输出口用时,每位能吸取电流的方式驱动8 个规律门电路,对端口写“1”可 作为高阻抗输入端用；在拜访外部数据储备器或程序储备器时,这组口线分时转换地址（低 8位）和数据总线复用,在拜访期间激活内部上拉电阻；P1口：P1是一个带内部上拉电阻的8 位双向 I/O 口,P1的输出缓冲级可驱动（吸取或输出电流） 4 个 TTL规律门电路；对端口写“1” ,通过内部的上拉电阻把端口拉到高电平, 此时可做熟出口； 做输出口使用时, 由于内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流（Iil）. Fl

46、ash 编程和程序校验期间, P1接受低 8 位地址；P2口：P2是一个带有内部上拉电阻的8 位双向 I/O 口,P2 的输出缓冲级可驱动（吸取或输出电流） 4 个 TTL 规律门电路；对端口写“1”,通过内部地山拉 电阻把端口拉到高电平, 此时可作为输出口, 作输出口使用时, 由于内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流（Iil）；在拜访外部程序储备器获 16 位地址的外部数据储备器（例如执行 MOVX DPTR指令）时,P2 口送出高 8 位地址数据； 在拜访 8 位地址的外部数据储备器（如执行 MOVX RI指令）时, P2 口线上的内容（也即特别功能寄存器（SFR）区中

47、 R2寄存器的内容）,在整个拜访期间不转变；Flash 编程或校验时, P2亦接受高地址和其它掌握信号；P3口：P3口是一组带有内部上拉电阻的8 位双向 I/O 口；P3 口输出缓冲级可驱动（吸取或输出电流）4 个 TTL规律门电路；对 P3口写入“1” 时,他们被内部上拉电阻拉高并可作为输出口；做输出端时,被外部拉低的 P3 口将用上拉电阻输出电流（ Iil）；P3 口除了作为一般的 I/O 口线外,更重要的用途是它的其次功能,如下表所示：端口引 其次功能脚P3.0 rxd 串行输入口 P3 口仍接收一P3.1 txd 串行输出口 P3.2 int0 外中断 0 P3.3 int1 外中断

48、1 些用于 flash闪速P3.4 t0 定时 / 计数器 0 储备器编程和程序P3.5 t1 定时 / 计数器 1 校验的掌握信号；RST： 复 位 输P3.6 WR 外部数据储备器写选通 入；当振荡器工作P3.7 RD 外部数据储备器读选通 时,RST引脚显现两个机器周期以上高电平将使单片机复位；ALE/PROG：当拜访外部程序储备器或数据储备器时,ALE（地址所存答应）输出脉冲用于所存地址的低 8 位字节；即使不拜访外部储备器,ALE仍以时钟振荡频率的 1/6 输出固定的正脉冲信号,因此它可对外输出时钟或用于定时目的；要留意的是：每当拜访外部数据储备器时将跳过一个 ALE脉冲；对 fla

49、sh 储备器编程期间,该引脚仍用于输入编程脉冲（PROG）；如有不要,可通过对特别功能寄存器（SFR）区中的 8EH单元的 D0位置位,可禁止 ALE操作；该外置位后, 只要一条 MOVX和 MOVC指令 ALE才会被激活； 此 外,该引脚会被柔弱拉高,单片机执行外部程序时,应设置 ALE无效；PSEN：程序储备答应（ PSEN）输出是外部程序储备器的读选通信号,当 at89s52 由外部程序储备器取指令 （或数据） 时,每个机器周期两个 PSEN有效,即输出两个脉冲；在此期间,当拜访外部数据储备器,这两次有效的 PSEN信号 不显现；EA/VPP:外 部 访 问 允 许 ； 欲 使 CPU

50、仅 访 问 外 部 程 序 存 储 器 （ 地 址 为 0000H-FFFFH）,EA端必需保持低电平（接地） ；需留意的是 ; 假如加密位 LB1 被编程,复位时内部会锁存 EA端状态；如 EA 端为高电平（接 VCC端）,CPU就执行内部程序储备器中的指令；Flash 储备器编程时,该引脚加上 +12V的编程答应电源 VPP,当然这必需是 该器件是使用 12V 编程电压 VPP. XTAL1: 振荡器反相放大器的及内部时钟发生器的输出端；XTAL2: 振荡器反相放大器的输出端；时钟振荡器 ：at89s52 中有一个用于构成内部振荡器的高增益反相放大器,引脚 XTAL1和XTAL2分别是该放

51、大器的输入端和输出端；这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器,振荡电路参见图 5；外接石英晶体（或陶瓷谐振器）及电容C1、C2 接在放大器的反馈回路中构成并联振荡电路；对外接电容 C1、C2虽然没有非常严格的要求,但电容容量的大小会稍微影响振荡频率的高低、振荡器的稳固性、 起振的难易程度及温度稳固性,假如使用石英晶体,我们举荐电容使用 30PF+10PF,而如使用陶瓷谐振器建议挑选 40PF+10PF；用户也可以采纳外部时钟； 采纳外部时钟的电路如图5 右所示；这种情形下,外部时钟脉冲接到 XTAL1端,即内部时钟发生器的输入端,XTAL2就悬空由于外部时钟信号是通过

52、一个 2 分频触发器后作为内部时钟信号的,所以对外部时钟信号的占空比没有特别要求,续时间应符合产品技术要求；但最小高电平连续时间和最大的低电平持闲暇模式 : 在闲暇工作模式状态,CPU保持睡眠状态而全部片内的外设仍保持激活状态,这种方式由软件产生； 此时,片内 RAM和全部特别功能寄存器的内容保持不 变；闲暇模式可由任何答应的中断恳求或硬件复位终止；终止闲暇工作模式的方法有两种,其一是任何一条被答应中断的大事被激 活,即可终止闲暇工作模式；程序会第一响应中断,进入中断服务程序,执行完 中断服务程序并仅随终端返回指令, 下一条要执行的指令就是使单片机进入闲暇 模式那条指令后面的一条指令；其二是通

53、过硬件复位也可将闲暇工作模式终止,需要留意的是,当由硬件复位来终止闲暇模式时,CPU通常是从激活闲暇模式那条指令的下一条指令开头连续执行程序的,要完成内部复位操作, 硬件复位脉冲 要保持两个机器周期（ 24 个时钟周期）有效,在这种情形下,内部禁止 CPU访 问片内 RAM,而答应拜访其它端口；为了防止可能对端口产生以外写入,激活空 闲模式的那条指令后一条指令不应当是一条对端口或外部储备器的写入指令；闲暇和掉电模式外部引脚状态模式程序储备器ALE PSEN PORT0 PORT1 PORT2 PORT3 闲暇模式内部1 1 数据数据数据数据闲暇模式外部1 1 浮空数据数据数据掉电模式内部0 0 数据数据数据数据掉电模式外部0 0 浮空数据数据数据掉电模式 : 在掉电模式下, 震荡器停止工作, 进入掉电模式的指令是最终一条被执行的 指令,片内 RAM和特别功能寄存器的内容在终止掉电模式前被冻结；退出掉电模 式的唯独方法是硬件复位, 复位后将重新定义全部特别功能寄存器但不转变 RAM中的内容, 在 VCC复原到正常工作电平前, 复位应无效, 且必需保持肯定时间以 使振荡重视启动并稳固工作；程序储备器的加密：AT89S52可使用